Chapter 3

Programmer’s Model

This chapter describes the ARM PrimeCell Generic Infrared Interface (PL140) registers and provides details needed when programming the microcontroller. It contains the following:

•About the programmer’s model on page 3-2

•Summary of PrimeCell GIR registers on page 3-3

•Register descriptions on page 3-4.

ARM DDI 0149B

© Copyright ARM Limited 1999. All rights reserved.

3-1

Programmer’s Model

3.1About the programmer’s model

The base address of the PrimeCell GIR is not fixed, and may be different for any particular system implementation. The offset of any particular register from the base address is fixed.

The following locations are reserved, and must not be used during normal operation:

•locations at offsets +0x1c–0x3c and +0xa4–0xff are reserved for possible future extensions

•locations at offsets +0x40 through +0xa0 are reserved for test purposes.

3-2

© Copyright ARM Limited 1999. All rights reserved.

ARM DDI 0149B

Programmer’s Model

3.2Summary of PrimeCell GIR registers

The PrimeCell GIR registers are shown in Table 3-1:

Table 3-1 PrimeCell GIR register summary

Address	Type	Width	Reset value	Name	Description
GIR Base + 0x00	Read/	15	0x0000	GIRFCR	Function control register.
	write
GIR Base + 0x04	Read/	16	0x0000	GIRTXGENCR	Transmit clock generator
	write				control register.
GIR Base + 0x08	Read/	16	0x0000	GIRRXGENCR	Receive clock generator
	write				control register.
GIR Base + 0x0c	Read/	4	0x0	GIRTXDUTYCR	Transmit carrier duty cycle
	write				register.
GIR Base + 0x10	Read	8	0x50	GIRSTAT	Status register.
GIR Base + 0x14	Read/	18/17	0x00000	GIRDATAR	Data register.
	write
GIR Base + 0x18	Read	3	0x0	GIRIIR	Interrupt identification
					register.
GIR Base + 0x18	Write	0	Undefined	GIRICR	Interrupt clear register.
GIR Base + 0x1c–0x3c	-	-	-	-	Reserved.
GIR Base + 0x40–0xa0	-	-	-	-	Reserved (for test purposes).
GIR Base + 0xa4–0xff	-	-	-	-	Reserved.

ARM DDI 0149B

© Copyright ARM Limited 1999. All rights reserved.

3-3