ARM PrimeCell Generic Infrared Interface (PL140) Signal Descriptions

A.1 AMBA APB signals

The PrimeCell GIR is connected to the AMBA APB bus as a bus slave. With the exception of the BnRES signal, the AMBA APB signals have a P prefix and are active HIGH. Active LOW signals are prefixed by a lower case n. The AMBA APB signals are described in Table A-1.

Table A-1 AMBA APB signal descriptions

	Name	Type	Source/	Description
			Destination
	PCLK	Input	Clock generator	AMBA APB clock, used to time all bus
				transfers.
	BnRES	Input	Reset controller	Bus reset signal, active LOW.
	PENABLE	Input	APB bridge	AMBA APB enable signal. PENABLE
				is asserted HIGH for one cycle of PCLK
				to enable a bus transfer.
	PSEL	Input	APB bridge	PrimeCell GIR select signal from
				decoder. When set to 1 this signal
				indicates the slave device is selected by
				the AMBA APB bridge, and that a data
				transfer is required.
	PWRITE	Input	APB bridge	AMBA APB transfer direction signal,
				indicates a write access when HIGH,
				read access when LOW.
	PADDR[7:2]	Input	APB bridge	Subset of AMBA APB address bus.
	PWDATA[31:0]	Input	APB bridge	Unidirectional AMBA APB write data
				bus.
	PRDATA [31:0]	Output	APB bridge	Unidirectional AMBA APB read data
				bus.

A-2

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ARM DDI 0149B

ARM PrimeCell Generic Infrared Interface (PL140) Signal

A.2 On-chip signals

The reset inputs are asynchronously asserted but synchronously removed for each of the clock domains within the PrimeCell GIR. This ensures that logic is reset even if clocks are not present, which avoids any static power consumption problems at power up. Each clock domain has a individual reset to simplify the process of inserting scan test cells.

The on-chip signals required in addition to the AMBA APB signals are shown in

Table A-2.

				Table A-2 On-chip signals
	Name	Type	Source/	Description
			Destination
	GIRCLK	Input	Clock generator	PrimeCell GIR reference clock input.
	nGIRRST	Input	Reset controller	PrimeCell GIR reset signal to GIRCLK
				clock domain, active LOW. The reset
				controller must use BnRES to assert
				nGIRRST asynchronously, but negate it
				synchronously with GIRCLK.
	GIRRORINTR	Input	Interrupt	Generic infrared receive overrun
			controller	interrupt.
	GIRRXINTR	Output	Interrupt	Generic infrared receive interrupt.
			controller
	GIRTXINTR	Output	Interrupt	Generic infrared transmit interrupt.
			controller
	GIRINTR	Output	Interrupt	Generic infrared interrupt. Asserted
			controller	when any of the above three interrupts
				are asserted.
	SCANMODE	Input	Test controller	PrimeCell GIR scan test mode input.
				This signal must be asserted HIGH
				during scan testing to ensure that internal
				data storage elements can be reset
				asynchronously.

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A-3

ARM PrimeCell Generic Infrared Interface (PL140) Signal Descriptions

A.3 Signals to pads

Table A-3 describes the signals from the PrimeCell GIR to input/output pads of the chip. It is the responsibility of the user to make proper use of the peripheral pins to meet the exact interface requirements.

				Table A-3 Signals to pads
	Name	Type	Source/	Description
			Destination
	GIRIN	Input	PAD	Generic infrared receive input.
				Input signal from an infrared
				photodetector or receiver. If the signal is
				from a simple detector, demodulation is
				usually required to recover the baseband
				signal.
	GIROUT	Output	PAD	Generic infrared transmit output.
				Output signal to infrared device. If the
				infrared device is a simple detector, the
				signal is usually modulated onto a
				carrier. Otherwise, the signal is a serial
				stream of baseband data, and modulation
				is performed off-chip.

A-4

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ARM DDI 0149B

Index

The items in this index are listed in alphabetic order, with symbols and numerics appearing at the end. The references given are to page numbers.

A

Address, base	3-2
AMBA
APB bus	A-2
APB interface		2-3
APB signals A-2
AMBA compatibility		1-4
ATPG 4-3

Automatic test pattern generation 4-3

B

Base address 3-2

Big-endian 1-4

BnRES A-2

C

Clocking mode 4-5

Compatibility,AMBA 1-4

D					GIRIN 2-2, A-4
Demodulator		2-5			GIRINTR	2-2, A-3
					GIROUT	2-2, A-4
E					GIRRORINTR		A-3
					GIRRXGENCR		3-7
External bus interface			4-2		GIRRXINTR		2-6, A-3
F					GIRSTAT	3-8
					GIRTCER	4-4
Functional description, GIR				2-3	GIRTDC	4-11
					GIRTISR	4-8
G					GIRTMR	4-6
					GIRTOCR	4-9
GIR
					GIRTRXCDC		4-10
features		1-2
					GIRTRXPTC		4-11
functional description				2-3
Integration Manual			1-4		GIRTTXC	4-10
overview		2-2			GIRTTXCDC		4-9
GIRCLK	2-2, 2-6, A-3
					GIRTXDUTYCR 3-8
GIRDATAR		3-9
					GIRTXGENCR		3-6
GIRFCR	3-4

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Index-i

Index
GIRTXINTR 2-6, A-3
I
Infrared methodology			2-7
Input filter and synchroniser				2-5
Input pin multiplexing			4-5
Interrupt generation logic				2-6
L
Little-endian 1-4
M
Multiplexing input pins			4-5
N
nGIRRST		A-3
P
PADDR		A-2
Pads	A-4
PCLK	2-6, A-2
PENABLE		A-2
PRDATA		A-2
Production testing 4-2
Programmer’s model			3-1
for test		4-1
PSEL	A-2
PWRITE		A-2

R

Receive and transmit clock divider 2-4

Receive demodulation		2-12
Receive FIFO	2-4
Receive logic	2-5
Receive processing		2-12
Receive pulse timer		2-5

Register

descriptions 3-4

summary	3-3
test 4-4
Register block	2-4

Revision E compatibility 1-4

S

Scan testing	4-3
SCANMODE	4-3, A-3

Signals A-4

Summary of registers 3-3

Synchronizing registers and logic 2-6

T

Test clock enable 4-4
Test harness	4-2
Test interface controller		4-2
Test registers	4-4
Test registers and logic		2-6
Testing 4-2
Transmit FIFO	2-4
Transmit logic	2-4

V

Verification	4-2
Virtual register	4-4

Index-ii

© Copyright ARM Limited 1999. All rights reserved.

ARM DDI 0149B