Programmer’s Model

3.3.4GIRTXDUTYCR: [4] (+ 0x0c)

GIRTXDUTYCR is the transmit carrier duty cycle control register which is used to control the duration of the HIGH phase of the transmitted carrier signal. Table 3-5 shows the bit assignments for the GIRTXDUTYCR.

			Table 3-5 GIRTXDUTYCR register read/write bits
Bits	Name	Type	Function
31:4	-	Read/write	Reserved, do not modify, read as 0.
3:0	high_phase	Read/write	Duration of the HIGH phase time of the carrier signal
			is (high_phase + 1)/16 of the period of the carrier
			signal:

0000 = Carrier HIGH time is 1/16 of period is invalid (see note).

0001 = Carrier HIGH time is 2/16 of period. 0010 = Carrier HIGH time is 3/16 of period.

...

1110 = Carrier HIGH time is 15/16 of period. 1111 = Reserved.

Note

The minimum HIGH phase duration supported is limited to 2/16 of the carrier period. A 1/16 carrier HIGH would be rejected by the 2-stage input filter in the receive logic.

3.3.5GIRSTAT: [8] (+0x10)

GIRSTAT is the status register which is a read-only register that contains status flags representing information about the current state of the PrimeCell GIR. Table 3-6 shows the bit assignments for the GIRSTAT.

		Table 3-6 GIRSTAT register read bits
Bits	Name	Type Function
31:8	-	Read Reserved, unpredictable when read.
7	RxFull	Read When set to 1 the receive FIFO is full.
6	TxEmpty	Read When set to 1 the transmit FIFO is empty.
5	TxFull	Read When set to 1 the transmit FIFO is full.

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		Table 3-6 GIRSTAT register read bits (continued)
Bits	Name	Type Function
4	RxEmpty	Read When set to 1 the receive FIFO is empty.
3	TxBusy	Read When set to 1 the transmitter is busy. Transmit
		function is enabled and a symbol is being transmitted.
2	RxBusy	Read When set to 1 the receiver is busy. Receive function is
		enabled and not timed out.
1	RxOverrun	Read When set to 1 the receive is overrun. (An attempt has
		been made to write to the receive FIFO, but it was
		full.)
0	RxTimeout	Read This bit is set HIGH to indicate that, while the
		receiver is enabled, the input has been stable for so
		long that the duration timer has advanced to its limit.

3.3.6GIRDATAR: [18/17] (+ 0x14c)

GIRDATAR is the data register which is used to transfer data to and from the PrimeCell GIR. A write operation to this location results in a write to the transmit FIFO. A read causes data to be read from the receive FIFO. The FIFOs are implemented as circular buffers controlled by read and write pointers. GIRDATAR is an 18-bit read register, but only 17 bits are written. Table 3-7 shows the bit assignments for the GIRDATAR.

			Table 3-7 GIRDATAR register read/write bits
Bits	Name	Type	Function
31:18	-	Read/write	Reserved, do not modify, read as 0.
17	-	Write	This bit is reserved in write mode, do not modify.
17	RXDataAvail	Read	In read mode, this bit reports whether the receive
			FIFO contains any more data after the current read
			has completed.

1 = More data to be read.

0 = Receive FIFO may be empty after the current read operation.

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Table 3-7 GIRDATAR register read/write bits (continued)

Bits	Name	Type	Function
16	txval/rxval	Read/write	In write mode, this bit gives the logic level of the bit
			to be transmitted.
			In read mode, this bit shows the logic level of the
			received bit.
15:0	data	Read/write	In write mode, these bits give the required duration
			(count value of transmit clock periods) of the
			transmitted bit. If modulation is enabled, a 1 is
			represented by a burst of carrier for the specified

time, otherwise the output will be an unmodulated logic level for the specified time.

In read mode these bits give the measured duration of the received bit.

Note

Software should take care not to write a data value whose bits 15 down to 0 are zero, into the transmit FIFO. This is because, if the bits 15 down to 0 are zero, it means that a pulse of zero width is to be transmitted which is invalid.

The successive data values programmed into the transmit FIFO should be of alternating data levels. If the successive data values are of the same level, the transmitter transmits both the data as a single data of a width which is equal to the sum of the values programmed into the FIFO. For example, if the data programmed into location 3 of transmit FIFO is 10 of logic level 1, and the data programmed into location 4 of transmit FIFO is 5 of logic level 1, then the transmitter sends it as a pulse width of 15 with logic level 1. If large values are written in this manner, then the receiver may overflow because of the very large value it receives.

3.3.7GIRIIR/GIRICR: [3/0] (+0x18)

GIRIIR is the interrupt identification register which is accessed when read. This register is read by the programmer to determine the interrupt source. This register is used when the common interrupt line is being used to signal an interrupt to the main device. After receiving an interrupt, the CPU may read this register to determine the source of the interrupt.

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GIRICR is the interrupt clear register which is accessed when written. Whenever the register is written the receive overrun interrupt is cleared irrespective of the value written to the register. Table 3-8 shows the bit assignments for the GIRIIR and GIRICR.

				Table 3-8 GIRIIR/GIRICR register read/write bits
Bits	Name	Type	Function
31:3	-	Read/write	Reserved, do not modify, read as 0.
2	TIS	Read	0 = Transmit section is not the interrupt source.
			1	= Transmit section is the interrupt source.
			This bit is set to 1 if the transmit interrupt GIRTXINTR is
			asserted.
1	RIS	Read	0	= Receive section is not the interrupt source.
			1	= Receive section is the interrupt source.
			This bit is set to 1 if the receive interrupt GIRRXINTR is
			asserted.
0	RORIS	Read	0	= Receive overrun section is not the interrupt source.
			1	= Receive overrun section is the interrupt source.
			This bit is set to 1 if the receive overrun interrupt
			GIRRORINTR is asserted.
0		Write	When this register is written, the receive overrun interrupt is
			cleared. Any value can be written.

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