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		Table 4-4 GIRTMR register read/write bits (continued)
Bit	Name	Description
0	RxTimerNibmode	1 = The 20-bit receive pulse timer is divided into nibbles for
		faster and more efficient testing. The test mode enables
		verification of counter functionality in less clock cycles since
		the counter is decremented by 0x11111 instead of 0x00001 as
		in normal mode.
		0 = Normal mode, the counter decrements by 1 for each
		enabled clock cycle.
		This bit is cleared to 0 by default on reset by BnRES.

4.3.4GIRTISR: [1] (+0x88)

GIRTISR is the test input stimulus register. It contains one bit (GIRRegRXD), which is used as the data bit to drive the receive data path in test mode. The bit is read/write as shown in Table 4-5.

		Table 4-5 GIRTISR register read/write bits
Bit	Name	Description
31:1		Reserved, unpredictable when read.
0	TestGIRIN	Programmable test stimulus for primary input GIRIN. This
		bit will have no effect when not in test mode.

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4.3.5GIRTOCR: [5] (+0x8c)

GIRTOCR is the test output capture register which is a 5-bit wide register that captures the non-AMBA outputs. The interrupt signals and the output signals are captured in this register. All the bits are read only and are assigned as shown in Table 4-6.

		Table 4-6 GIRTOCR register read bits
Bit	Name	Description
31:5		Reserved, unpredictable when read.
4	TGIRINTR	This bit is HIGH if GIRINTR is HIGH. GIRINTR is HIGH
		if GIRTXINTR, GIRRXINTR or GIRRRORINTR is
		HIGH.
		This bit is cleared to 0 by default on reset by BnRES.
3	TGIRORINTR	This bit is HIGH when GIRRORINTR is asserted, otherwise
		it is LOW.
		This bit is cleared to 0 by default on reset by BnRES.
2	TGIRRXINTR	This bit is HIGH when GIRRXINTR is asserted, otherwise it
		is LOW.
		This bit is cleared to 0 by default on reset by BnRES.
1	TGIRTXINTR	This bit is HIGH when GIRTXINTR is asserted, otherwise it
		is LOW.
		This bit is cleared to 0 by default on reset by BnRES.
0	TGIROUT	This bit represents the logic level on the GIROUT pin.
		This bit is cleared to 0 by default on reset by BnRES.

4.3.6GIRTTXCDC [16] (+0x90)

GIRTTXCDC is a read-only register that returns the current value of the 16-bit transmit clock divider used to generate the transmit clock from the GIRCLK. Table 4-7 shows the bit assignments for the GIRTTXCDC.

		Table 4-7 GIRTTXCDC register bits read bits
Bit	Name	Description
31:16	-	Reserved, unpredictable when read.
15:0	TXCDC	Reading this register returns the current value of the transmit clock
		divide counter.

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4.3.7GIRTRXCDC [16] (+0x94)

GIRTRXCDC is a read-only register that returns the current value of the 16-bit receive clock divider used to generate the receive clock from the GIRCLK. Table 4-8 shows the bit assignments for the GIRTRXCDC.

		Table 4-8 GIRTRXCDC register bits read bits
Bit	Name	Description
31:16	-	Reserved, unpredictable when read.
15:0	RXCDC	Reading this register returns the current value of the receive clock
		divide counter.

4.3.8GIRTTXC [20] (+0x98)

GIRTTXC is a read-only register that returns the current value of the 20-bit counter value used to generate the transmit output signal. Table 4-9 shows the bit assignments for the GIRTTXC.

		Table 4-9 GIRTTXC register bits read bits
Bit	Name	Description
31:20	-	Reserved, unpredictable when read.
19:0	TXC	Reading this register returns the current value of the transmit timer
		counter.

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4.3.9GIRTRXPTC [20] (+0x9c)

GIRTRXPTC is a read-only register that returns the current value of the 20-bit pulse timer used to measure the received signal. Table 4-10 shows the bit assignments for the GIRTRXPTC.

		Table 4-10 GIRTRXPTC register bits read bits
Bit	Name	Description
31:20	-	Reserved, unpredictable when read.
19:0	RXPTC	Reading this register returns the current value of the receive pulse
		timer counter.

4.3.10GIRTDC [7] (+0xa0)

GIRTDC is a read-only register that returns the current value of the 7-bit demodulator counter used to demodulate the input signal. Table 4-11 shows the bit assignments for the GIRTDC.

		Table 4-11 GIRTDC register bits read bits
Bit	Name	Description
31:7		Reserved, unpredictable when read.
6:0	TDC	Reading this register returns the current value of the receive
		demodulation counter.

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Appendix A

ARM PrimeCell Generic Infrared Interface

(PL140) Signal Descriptions

This appendix describes the signals that interface with the ARM PrimeCell Generic Infrared Interface (PL140). It contains the following:

•AMBA APB signals on page A-2

•On-chip signals on page A-3

•Signals to pads on page A-4.

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A-1