Chapter 8: XST Behavioral Verilog Language Support

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Behavioral Verilog While Loops

When using always blocks, use the while statement to execute repetitive procedures. A while loop executes other statements until its test expression becomes false. It is not executed if the test expression is initially false.

•The test expression is any valid Verilog expression.

•To prevent endless loops, use the -loop_iteration_limit option.

•While loops can have disable statements. The disable statement is used inside a labeled block, since the syntax is disable <blockname>.

Behavioral Verilog While Loop Coding Example

parameter P = 4; always @(ID_complete)

begin : UNIDENTIFIED integer i;

reg found; unidentified = 0; i = 0;

found = 0;

while (!found && (i < P)) begin

found = !ID_complete[i]; unidentified[i] = !ID_complete[i]; i = i + 1;

end

end

Behavioral Verilog Sequential Always Blocks

Sequential circuit description is based on always blocks with a sensitivity list. The sensitivity list contains a maximum of three edge-triggered events:

•A clock signal event (mandatory)

•A reset signal event (possibly)

•A set signal event

One, and only one, if...else statement is accepted in such an always block.

An asynchronous part may appear before the synchronous part in the first and the second branch of the if...else statement. Signals assigned in the asynchronous part are assigned to the following constant values:

•0

•1

•X

•Z

•any vector composed of these values

These same signals are also assigned in the synchronous part (that is, the last branch of the if...else statement). The clock signal condition is the condition of the last branch of the if...else statement.

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Behavioral Verilog Procedural Assignments

8 Bit Register Using an Always Block Behavioral Verilog Coding Example

module seq1 (DI, CLK, DO); input [7:0] DI;

input CLK; output [7:0] DO; reg [7:0] DO;

always @(posedge CLK) DO <= DI ;

8 Bit Register with Asynchronous Reset (High-True) Using an Always Block Behavioral Verilog Coding Example

module EXAMPLE (DI, CLK, RST, DO); input [7:0] DI;

input CLK, RST; output [7:0] DO; reg [7:0] DO;

always @(posedge CLK or posedge RST) if (RST == 1'b1)

DO <= 8'b00000000; else

DO <= DI; endmodule

8 Bit Counter with Asynchronous Reset (Low-True) Using an Always Block Behavioral Verilog Coding Example

module seq2 (CLK, RST, DO); input CLK, RST;

output [7:0] DO; reg [7:0] DO;

always @(posedge CLK or posedge RST) if (RST == 1'b1)

DO <= 8'b00000000; else

DO <= DO + 8'b00000001; endmodule

Behavioral Verilog Assign and Deassign Statements

Assign and deassign statements are supported within simple templates.

Behavioral Verilog Assign and Deassign Statements General Template Coding Example

module assig (RST, SELECT, STATE, CLOCK, DATA_IN); input RST;

input SELECT; input CLOCK;

input [0:3] DATA_IN; output [0:3] STATE; reg [0:3] STATE;

always @ (RST) if(RST)

begin

assign STATE = 4'b0;

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end else

begin

deassign STATE; end

always @ (posedge CLOCK) begin

STATE <= DATA_IN; end

endmodule

The main limitations on support of the assign/deassign statement in XST are:

•For a given signal, there is only one assign/deassign statement.

•The assign/deassign statement is performed in the same always block through an if/else statement.

•You cannot assign a bit/part select of a signal through an assign/deassign statement.

Behavioral Verilog Assign/Deassign Statement Coding Example

For a given signal, there is only one assign/deassign statement. For example, XST rejects the following design:

module dflop (RST, SET, STATE, CLOCK, DATA_IN); input RST;

input SET; input CLOCK; input DATA_IN; output STATE; reg STATE;

always @ (RST)	// block b1
if(RST)
assign STATE = 1'b0;
else
deassign STATE;
always @ (SET)	// block b1
if(SET)
assign STATE = 1'b1;
else
deassign STATE;
always @ (posedge CLOCK)	// block b2
begin
STATE <= DATA_IN;
end
endmodule

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Behavioral Verilog Procedural Assignments

Behavioral Verilog Assign/Deassign Statement Performed in Same Always

Block

The assign/deassign statement is performed in the same always block through an if...else statement. For example, XST rejects the following design:

module dflop (RST, SET, STATE, CLOCK, DATA_IN); input RST;

input SET; input CLOCK; input DATA_IN; output STATE;

reg STATE;
always @ (RST or SET)	// block b1
case ({RST,SET})

2'b00: assign STATE = 1'b0; 2'b01: assign STATE = 1'b0; 2'b10: assign STATE = 1'b1; 2'b11: deassign STATE;

endcase
always @ (posedge CLOCK)	// block b2
begin
STATE <= DATA_IN;
end
endmodule

Cannot Assign Bit/Part Select of Signal Through Assign/Deassign Statement

You cannot assign a bit/part select of a signal through an assign/deassign statement. For example, XST rejects the following design:

module assig (RST, SELECT, STATE, CLOCK, DATA_IN); input RST;

input SELECT; input CLOCK;

input [0:7] DATA_IN; output [0:7] STATE;

reg [0:7] STATE;
always @ (RST)	// block b1
if(RST)
begin

assign STATE[0:7] = 8'b0; end

else begin

deassign STATE[0:7];

end
always @ (posedge	CLOCK)	// block b2
begin
if (SELECT)
STATE [0:3]	<= DATA_IN[0:3];
else
STATE [4:7]	<= DATA_IN[4:7];

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