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Chapter 9

XST Mixed Language Support

This chapter (XST Mixed Language Support) describes how to run an XST project that mixes Verilog and VHDL designs. This chapter includes:

•“About Mixed Language Support”

•“Mixed Language Project Files”

•“VHDL and Verilog Boundary Rules in Mixed Language Projects”

•“Port Mapping in Mixed Language Projects”

•“Generics Support in Mixed Language Projects”

•“Library Search Order (LSO) Files in Mixed Language Projects”

About Mixed Language Support

XST supports mixed VHDL and Verilog projects.

•Mixing VHDL and Verilog is restricted to design unit (cell) instantiation only.

♦A VHDL design can instantiate a Verilog module

♦A Verilog design can instantiate a VHDL entity.

♦No other mixing between VHDL and Verilog is not supported.

•In a VHDL design, a restricted subset of VHDL types, generics, and ports is allowed on the boundary to a Verilog module.

•In a Verilog design, a restricted subset of Verilog types, parameters, and ports is allowed on the boundary to a VHDL entity or configuration.

•XST binds VHDL design units to a Verilog module during the Elaboration step.

•Component instantiation based on default binding is used for binding Verilog modules to a VHDL design unit.

•Configuration specification, direct instantiation and component configurations are not supported for a Verilog module instantiation in VHDL.

•VHDL and Verilog project files are unified.

•VHDL and Verilog libraries are logically unified.

•Specification of the work directory for compilation (xsthdpdir), previously available only for VHDL, is now available for Verilog.

•The xhdp.ini mechanism for mapping a logical library name to a physical directory name on the host file system, previously available only for VHDL, is also available for Verilog.

XST User Guide

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