Chapter 9: XST Mixed Language Support

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Language Projects.” If found, XST binds the name. XST selects the first VHDL entity matching the name, and binds it.

XST has the following limitations when instantiating a VHDL design unit from a Verilog module:

•Use explicit port association. Specify formal and effective port names in the port map.

•All parameters are passed at instantiation, even if they are unchanged.

•The parameter override is named and not ordered. The parameter override occurs through instantiation, and not through defparams.

Correct Use of Parameter Override Coding Example

ff #(.init(2'b01)) u1 (.sel(sel), .din(din), .dout(dout));

Correct Use of Parameter Override Coding Example

The following example is not accepted by XST.

ff u1 (.sel(sel), .din(din), .dout(dout)); defparam u1.init = 2'b01;

Port Mapping in Mixed Language Projects

This section discusses Port Mapping in Mixed Language Projects, and includes:

•“VHDL in Verilog Port Mapping”

•“Verilog in VHDL Port Mapping”

•“VHDL in Mixed Language Port Mapping”

•“Verilog in Mixed Language Port Mapping”

VHDL in Verilog Port Mapping

For VHDL entities instantiated in Verilog designs, XST supports the following port types:

•in

•out

•inout

XST does not support VHDL buffer and linkage ports.

Verilog in VHDL Port Mapping

For Verilog modules instantiated in VHDL designs, XST supports the following port types:

•input

•output

•inout

XST does not support connection to bi-directional pass options in Verilog.

XST does not support unnamed Verilog ports for mixed language boundaries.

Use an equivalent component declaration for connecting to a case sensitive port in a

Verilog module. By default, XST assumes Verilog ports are in all lower case.

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