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Implementation Constraints

number of ports in a timing report represent the number of destination elements for a timing constraint.

For example, if you use the following timing constraints:

TIMESPEC "TSidentifier"=FROM "source_group" TO "dest_group" value units;

then the number of ports corresponds to the number of elements in the destination group.

For a given timing constraint, XST may report that the number of failed paths is 100, but that the number of failed destination ports is only two flip-flops. In that case, it is sufficient to analyze the design description for these two flip-flops only in order to detect the changes necessary to meet timing.

Implementation Constraints

XST writes all implementation constraints generated from HDL or constraint file attributes (LOC, ...) into the output NGC file.

“Keep (KEEP)” properties are generated during buffer insertion for maximum fanout control or for optimization.

Virtex Primitive Support

This section discusses Virtex Primitive Support, and includes:

•“Instantiating Virtex Primitives”

•“Generating Primitives Through Attributes”

•“Primitives and Black Boxes”

•“VHDL and Verilog Virtex Libraries”

•“Virtex Primitives Log File”

•“Virtex Primitives Related Constraints”

•“Virtex Primitives Coding Examples”

•“Using the UNIMACRO Library”

Instantiating Virtex Primitives

XST enables you to instantiate Virtex primitives directly in your VHDL or Verilog code. Virtex primitives such as the following can be manually inserted in your HDL design through instantiation:

•MUXCY_L

•LUT4_L

•CLKDLL

•RAMB4_S1_S16

•IBUFG_PCI33_5

•NAND3b2

All these primitives are compiled in the UNISIM library.

These primitives are not optimized by XST by default, and are available in the final NGC file. Use the Optimize Instantiated Primitives synthesis option to optimize instantiated

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primitives and obtain better results. Timing information is available for most of the primitives, allowing XST to perform efficient timing-driven optimization.

In order to simplify instantiation of complex primitives as RAMs, XST supports an additional library called UNIMACRO. For more information, see the Xilinx Libraries Guides at http://www.xilinx.com/support/software_manuals.htm.

Generating Primitives Through Attributes

Some of these primitives can be generated through attributes:

•“Buffer Type (BUFFER_TYPE)” can be assigned to the primary input or internal signal to force the use of BUFGDLL, IBUFG, BUFR or BUFGP. The same constraints can be used to disable buffer insertion.

•“I/O Standard (IOSTANDARD)” can be used to assign an I/O standard to an I/O primitive. For example, the following assigns PCI33_5 I/O standard to the I/O port:

// synthesis attribute IOSTANDARD of in1 is PCI33_5

Primitives and Black Boxes

The primitive support is based on the concept of the black box. For information on the basics of black box support, see “Safe FSM Implementation.”

There is a significant difference between black box and primitive support. Assume you have a design with a submodule called MUXF5. In general, the MUXF5 can be your own functional block or a Virtex primitive. To avoid confusion about how XST interprets this module, attach “BoxType (BOX_TYPE)” to the component declaration of MUXF5.

If “BoxType (BOX_TYPE)” is attached to the MUXF5 with a value of:

•primitive, or black_box

XST tries to interpret this module as a Virtex primitive and use its parameters, for instance, in critical path estimation.

•user_black_box

XST processes it as a regular user black box.

If the name of the user black box is the same as that of a Virtex primitive, XST renames it to a unique name and issues a warning. For example, MUX5 could be renamed to MUX51 as shown in the following log file example:

...

================================================================

* Low Level Synthesis *

================================================================

WARNING:Xst:79 - Model 'muxf5' has different characteristics in destination library

WARNING:Xst:80 - Model name has been changed to 'muxf51'

...

If “BoxType (BOX_TYPE)” is not attached to the MUXF5, XST processes this block as a user hierarchical block. If the name of the user black box is the same as that of a Virtex primitive, XST renames it to a unique name and issues a warning.

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VHDL and Verilog Virtex Libraries

This section discusses VHDL and Verilog Virtex Libraries, and includes:

•“About VHDL and Verilog Virtex Libraries”

•“VHDL Virtex Libraries”

•“Verilog Virtex Libraries”

About VHDL and Verilog Virtex Libraries

To simplify instantiation, XST includes VHDL and Verilog Virtex libraries. These libraries contain the complete set of Virtex primitives declarations with a “BoxType (BOX_TYPE)” constraint attached to each component.

VHDL Virtex Libraries

In VHDL, declare library unisim with its package vcomponents in your source code:

library unisim;

use unisim.vcomponents.all;

The source code of this package can be found in the vhdl\src\ unisims\unisims_vcomp.vhd file of the XST installation.

Verilog Virtex Libraries

In Verilog, the unisim library is precompiled. XST automatically links it with your design.

Use UPPERCASE for generic (VHDL) and parameter (Verilog) values when instantiating primitives.

For example the ODDR element has the following component declaration in UNISIM library:

component ODDR generic

(DDR_CLK_EDGE : string := "OPPOSITE_EDGE"; INIT : bit := '0';

SRTYPE : string := "SYNC");

port(Q : out std_ulogic; C : in std_ulogic; CE : in std_ulogic; D1 : in std_ulogic; D2 : in std_ulogic; R : in std_ulogic; S : in std_ulogic);

end component;

When you instantiate this primitive in your code, the values of DDR_CLK_EDGE and SRTYPE generics must be in uppercase. If not, XST issues a warning stating that unknown values are used.

Some primitives, such as LUT1, enable you to use an INIT during instantiation. The two ways to pass an INIT to the final netlist are:

•Attach an INIT attribute to the instantiated primitive.

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•Pass the INIT with the generics mechanism (VHDL), or the parameters mechanism (Verilog). Xilinx recommends this method, since it allows you to use the same code for synthesis and simulation.

Virtex Primitives Log File

XST does not issue any message concerning instantiation of Virtex primitives during HDL synthesis because the “BoxType (BOX_TYPE)” attribute with its value, primitive, is attached to each primitive in the UNISIM library.

If you instantiate a block (non primitive) in your design and the block has no contents (no logic description) or the block has a logic description, but you attach a “BoxType (BOX_TYPE)” constraint to it with a value of user_black_box, XST issues a warning as shown in the following log file example:

...

Analyzing Entity <black_b> (Architecture <archi>).

WARNING : (VHDL_0103). c:\jm\des.vhd (Line 23). Generating a Black Box for component <my_block>.

Entity <black_b> analyzed. Unit <black_b> generated.

...

Virtex Primitives Related Constraints

•“BoxType (BOX_TYPE)”

•The PAR constraints that can be passed from HDL to NGC without processing

Virtex Primitives Coding Examples

This section gives the following Virtex Primitives coding examples:

•“Passing an INIT Value Via the INIT Constraint VHDL Coding Example”

•“Passing an INIT Value Via the INIT Constraint Verilog Coding Example”

•“Passing an INIT Value Via the Generics Mechanism VHDL Coding Example”

•“Passing an INIT Value Via the Parameters Mechanism Verilog Coding Example”

•“Passing an INIT Value Via the Defparam Mechanism Verilog Coding Example”

The coding examples in this section are accurate as of the date of publication. Download updates from ftp://ftp.xilinx.com/pub/documentation/misc/examples_v9.zip.

Passing an INIT Value Via the INIT Constraint VHDL Coding Example

--

-- Passing an INIT value via the INIT constraint.

--

library ieee;

use ieee.std_logic_1164.all;

library unisim;

use unisim.vcomponents.all;

entity primitive_1 is port(I0,I1 : in std_logic;

O : out std_logic); end primitive_1;

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architecture beh of primitive_1 is

attribute INIT: string;

attribute INIT of inst: label is "1";

begin

inst: LUT2 port map (I0=>I0,I1=>I1,O=>O);

end beh;

Passing an INIT Value Via the INIT Constraint Verilog Coding Example

//

// Passing an INIT value via the INIT constraint.

//

module v_primitive_1 (I0,I1,O); input I0,I1;

output O;

(* INIT="1" *)

LUT2 inst (.I0(I0), .I1(I1), .O(O));

endmodule

Passing an INIT Value Via the Generics Mechanism VHDL Coding Example

--

-- Passing an INIT value via the generics mechanism.

--

library ieee;

use ieee.std_logic_1164.all;

library unisim;

use unisim.vcomponents.all;

entity primitive_2 is port(I0,I1 : in std_logic;

O : out std_logic); end primitive_2;

architecture beh of primitive_2 is begin

inst: LUT2 generic map (INIT=>"1") port map (I0=>I0,I1=>I1,O=>O);

end beh;

Passing an INIT Value Via the Parameters Mechanism Verilog Coding Example

//

// Passing an INIT value via the parameters mechanism.

//

module v_primitive_2 (I0,I1,O); input I0,I1;

output O;

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