R

Flip-Flop Retiming

module v_logic_bram_2 (clk, rst, A, B, RES);

input	clk, rst;
input	[3:0] A, B;
output	[3:0] RES;
reg	[3:0] RES;
always	@(posedge clk or posedge rst)
begin
if	(rst)
	RES <= 4'b0000;

else

RES <= A + B + 8'b0001;

end

endmodule

Flip-Flop Retiming

This section discusses Flip-Flop Retiming, and includes:

•“About Flip-Flop Retiming”

•“Limitations of Flip-Flop Retiming”

•“Controlling Flip-Flop Retiming”

About Flip-Flop Retiming

Flip-flop retiming consists of moving flip-flops and latches across logic for the purpose of improving timing, thus increasing clock frequency.

Flip-flop retiming can be either forward or backward:

•Forward retiming moves a set of flip-flops that are the input of a LUT to a single flipflop at its output.

•Backward retiming moves a flip-flop that is at the output of a LUT to a set of flip-flops at its input.

Flip-flop retiming can:

•Significantly increase the number of flip-flops

•Remove some flip-flops

Nevertheless, the behavior of the designs remains the same. Only timing delays are modified.

Flip-flop retiming is part of global optimization. It respects the same constraints as all other optimization techniques. Since retiming is iterative, a flip-flop that is the result of a retiming can be moved again in the same direction (forward or backward) if it results in better timing. The only limit for the retiming occurs when the timing constraints are satisfied, or if no more improvements in timing can be obtained.

For each flip-flop moved, a message is printed specifying:

•The original and new flip-flop names

•Whether it is a forward or backward retiming.

XST User Guide

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