R

Chapter 2

XST HDL Coding Techniques

This chapter (XST HDL Coding Techniques) gives Hardware Description Language (HDL) coding examples for digital logic circuits. This chapter includes:

•“Signed and Unsigned Support in XST”

•“Registers HDL Coding Techniques”

•“Latches HDL Coding Techniques”

•“Tristates HDL Coding Techniques”

•“Counters HDL Coding Techniques”

•“Accumulators HDL Coding Techniques”

•“Shift Registers HDL Coding Techniques”

•“Dynamic Shift Registers HDL Coding Techniques”

•“Multiplexers HDL Coding Techniques”

•“Decoders HDL Coding Techniques”

•“Priority Encoders HDL Coding Techniques”

•“Logical Shifters HDL Coding Techniques”

•“Arithmetic Operators HDL Coding Techniques”

•“Adders, Subtractors, and Adders/Subtractors HDL Coding Techniques”

•“Comparators HDL Coding Techniques”

•“Multipliers HDL Coding Techniques”

•“Sequential Complex Multipliers HDL Coding Techniques”

•“Pipelined Multipliers HDL Coding Techniques”

•“Multiply Adder/Subtractors HDL Coding Techniques”

•“Multiply Accumulate HDL Coding Techniques”

•“Dividers HDL Coding Techniques”

•“Resource Sharing HDL Coding Techniques”

•“RAMs and ROMs HDL Coding Techniques”

•“Pipelined Distributed RAM HDL Coding Techniques”

•“Finite State Machines (FSMs) HDL Coding Techniques”

•“Black Boxes HDL Coding Techniques”

Most sections include:

•A general description of the macro

•A sample log file

XST User Guide

www.xilinx.com

23

10.1

Chapter 2: XST HDL Coding Techniques

R

•Constraints you can use to control the macro processing in XST

•VHDL and Verilog coding examples, including a schematic diagram and pin descriptions

For more information, see “XST FPGA Optimization” and “XST CPLD Optimization.”

For information on accessing the synthesis templates from Project Navigator, see the ISE™ Help.

Signed and Unsigned Support in XST

When using Verilog or VHDL in XST, some macros, such as adders or counters, can be implemented for signed and unsigned values.

To enable support for signed and unsigned values in Verilog, enable Verilog-2001 as follows:

•In Project Navigator, select Verilog 2001 as instructed in the Synthesis Options topic of ISE Help, or

•Set the -verilog2001 command line option to yes.

For VHDL, depending on the operation and type of the operands, you must include additional packages in your code. For example, to create an unsigned adder, use the arithmetic packages and types that operate on unsigned values shown in Table 2-1, “Unsigned Adder.”

Table 2-1: Unsigned Adder

PACKAGE	TYPE
numeric_std	unsigned
std_logic_arith	unsigned
std_logic_unsigned	std_logic_vector

To create a signed adder, use the arithmetic packages and types that operate on signed values shown in Table 2-2, “Signed Adder.”

Table 2-2: Signed Adder

PACKAGE	TYPE
numeric_std	signed
std_logic_arith	signed
std_logic_signed	std_logic_vector

For more information about available types, see the IEEE VHDL Manual.

24	www.xilinx.com	XST User Guide
		10.1