Timer

4.2Timer Operation

The timer is loaded by writing to the Load register and then, if enabled, the timer will count down to zero. On reaching a count of zero an interrupt will be generated. The interrupt may be cleared by writing to the Clear register.

After reaching a zero count, if the timer is operating in free-running mode then the timer will continue to decrement from its maximum value. If periodic timer mode is selected then the timer will reload from the Load register and continue to decrement. In this mode the timer will effectively generate a periodic interrupt. The mode is selected by a bit in the Control register.

At any point the current timer value may be read from the Value register.

The timer is enabled by a bit in the control register. At reset the timer will be disabled, the interrupt will be cleared and the Load register will be undefined. The mode and pre-scale value will also be undefined.

		Load	Control
		Load Register	Control Register
	Timer	16 bit Down Counter	Terminal Count
	Clock
			Interrupt
		Value

Figure 4-1: Timer Block Diagram

The timer clock is generated by a pre-scale unit. The timer clock may be the system clock, the system clock divided by 16, which is generated by 4 bits of pre-scale, or the system clock divided by 256, which is generated by a total of 8 bits of pre-scale.

		Reference Peripherals Specification	4-3
		ARM DDI 0062D

Open Access

Timer

Pre-scale Unit

Divide

Divide

System

Clock

by 16

by 16

Timer

Clock

Pre-scale

Select

Figure 4-2: Timer Pre-scale Unit

4-4	Reference Peripherals Specification
	ARM DDI 0062D

Open Access