Interrupt Controller

3.2Interrupt Control

The interrupt controller provides interrupt source status, interrupt request status and an enable register. The enable register is used to determine if an active interrupt source should generate an interrupt request to the processor.

The interrupt source status indicates if the appropriate interrupt source is active prior to masking. The interrupt source shall be active HIGH and therefore a logic HIGH in the source status register indicates that the interrupt source is active.

The interrupt request status indicates if the interrupt source will generate an interrupt request to the processor.

The enable register has a dual mechanism for setting and clearing the enable bits. This allows enable bits to be set or cleared independently, with no knowledge of the other bits in the enable register.

When writing to the enable set location, each data bit that is high will set the corresponding bit in the enable register and all other bits of the enable register will be unaffected. The enable clear location is conversely used to clear bits in the enable register while leaving other bits unaffected.

Figure 3-2: Interrupt Controller Bit Slice below shows a single bit-slice of the interrupt controller.

Enable Set
			Set				Enable
Enable Clear
			Clear

nterrupt

Interrupt Request

Source

Source Status

					nIRQ
	Other Interrupt Bit Slices
	Figure 3-2: Interrupt Controller Bit Slice
3-4	Reference Peripherals Specification
				ARM DDI 0062D

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Interrupt Controller

The FIQ interrupt controller consists of a single bit slice, located on bit 0. The IRQ controller, however, will have a larger number of bit slices, the exact size being dependent on the system implementation.

		Reference Peripherals Specification	3-5
		ARM DDI 0062D

Open Access