Interrupt Controller
3.5Interrupt Controller Memory Map
The base address of the Interrupt Controller is not fixed and may be different for any particular system implementation. However, the offset of any particular register from the base address is fixed.
Address |
Read Location |
Write Location |
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IntBase + 0x00 |
IRQStatus |
Reserved |
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IntBase + 0x04 |
IRQRawStatus |
Reserved |
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IntBase + 0x08 |
IRQEnable |
IRQEnableSet |
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ntBase + 0x0C |
Reserved |
IRQEnableClear |
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IntBase + 0x10 |
Reserved |
IRQSoft |
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IntBase + 0x100 |
FIQStatus |
Reserved |
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IntBase + 0x104 |
FIQRawStatus |
Reserved |
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IntBase + 0x108 |
FIQEnable |
FIQEnableSet |
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IntBase + 0x10C |
Reserved |
FIQEnableClear |
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Table 3-2: Interrupt Controller Memory Map
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Reference Peripherals Specification |
3-9 |
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ARM DDI 0062D |
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Open Access
Interrupt Controller
3-10 |
Reference Peripherals Specification |
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ARM DDI 0062D |
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Open Access
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4 |
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Timer |
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4.1 |
Introduction |
4-2 |
4.2 |
Timer Operation |
4-3 |
4.3 |
Timer Register Descriptions |
4-5 |
4.4 |
Timer Memory Map |
4-7 |
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Reference Peripherals Specification |
4-1 |
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ARM DDI 0062D |
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Open Access