Introduction
1.2Summary
This document describes a number of functional blocks that make up the set of Reference Peripherals.
The specification gives details for the following elements of a system:
Memory Map |
Flexible memory map with variable block base |
|
addresses. |
|
Fixed offsets from functional block base |
|
addresses. |
|
See Chapter 2, Memory Map. |
Interrupt Controller |
Source status and interrupt request status |
|
available. |
|
Separate enable set and enable clear |
|
registers allows independent bit enable |
|
control of interrupt sources. |
|
Level sensitive interrupts. |
|
Programmed interrupt source available |
|
See Chapter 3, Interrupt Controller. |
Timers |
Two 16 bit down count timers. |
|
Selectable clock source, normal, ÷16 or ÷256. |
|
Free-running or periodic timer modes. |
|
See Chapter 4, Timer. |
Communications Channel |
Defined transmit and receive interrupt |
|
mechanism. |
|
See Chapter 5, Communications Channel. |
Reset and Pause Controller |
Defined Boot Behavior with Power-On Reset |
|
detection. |
|
"Wait for Interrupt" Pause mode. |
|
Identification Register. |
|
See Chapter 6, Remap and Pause. |
A definition of the ARM core used within the system is not included as this is independent of the system programmer's model.
|
|
Reference Peripherals Specification |
1-3 |
|
|
ARM DDI 0062D |
|
|
|
|
|
Open Access
Introduction
1-4 |
Reference Peripherals Specification |
|
|
|
ARM DDI 0062D |
|
|
|
|
|
|
Open Access
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2 |
|
Memory Map |
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2.1 |
Introduction |
2-2 |
2.2 |
Memory Map Base Addresses |
2-3 |
|
|
Reference Peripherals Specification |
2-1 |
|
|
ARM DDI 0062D |
|
|
|
|
|
Open Access