Remap and Pause

6.1Introduction

The Remap and Pause control is the combination of four separate functions, Pause, Identification Register, Reset Status and Reset Memory Map, which are described in this chapter.

6-2	Reference Peripherals Specification
	ARM DDI 0062D

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Remap and Pause

6.2Pause

The Pause control simply defines a method of allowing the processor system to enter a lowpower “wait for interrupt” state, where the system does not require the processor to be active.

The Pause location is write only. Writing to the Pause location causes the system to enter the "wait for interrupt" state.

The exact effect of writing to this location is not defined, but typically it would prevent the processor from fetching further instructions until it recieves an interrupt.

		Reference Peripherals Specification	6-3
		ARM DDI 0062D

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Remap and Pause

6.3Identification Register

The Identification (ID) register provides an indication of the system configuration.

The ID register is read only. Only a single bit implementation is required, bit 0, which is used to indicate whether there is any further ID information.

ID Bit 0 is the Identification Bit which may be set to:

•0—no Further ID Information

•1—further ID Information is available

If the bottom bit of the ID register is set, then further bits are required to provide more detailed system identification information.

6-4	Reference Peripherals Specification
	ARM DDI 0062D

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Remap and Pause

6.4Reset Status

The Reset Status Register indicates the cause of the most recent reset condition—a minimum implementation is defined below.

The Reset Status Register is read only. Only one bit of this register defined in this specification, the Power On Reset bit. This bit may be used to determine if the most recent reset was caused by initial power on, or if a warm reset has occurred. The Power On Reset bit is bit 0 of the Reset Status Register, and may take the values:

•0—no POR since flag was lasted cleared

•1—POR

Further bits in the reset status register may be implemented to provide more detailed reset information.

The status register has a dual mechanism for setting and clearing bits, allowing independent bits to be altered with no knowledge of the other bits in the register.

The Reset Status Clear location is write only. This location is used to clear Reset Status flags. When writing to this register each data bit which is high will cause the corresponding bit in the Reset Status register to be cleared. Data bits which are low have no effect on the corresponding bit in the Reset Status register.

The Reset Status Set location is write only. This location is used to set Reset Status flags. When writing to this register each data bit which is high will cause the corresponding bit in the Reset Status register to be set. Data bits which are low have no effect on the corresponding bit in the Reset Status register.

The Reset Status set location has no function in the minimal Reference Peripherals specification, because the Power On Reset status bit cannot be set by software. This register is included in the specification to ensure expandability of the reset status functionality.

		Reference Peripherals Specification	6-5
		ARM DDI 0062D

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