8XC196Kx, Jx, CA USER’S MANUAL

PTS Block Transfer Mode Control Block (Continued)

Register	Location						Function
PTSCON	PTSCB + 1	PTS Control Bits
		M2:0	PTS Mode
			These bits select the PTS mode:
			M2		M1	M0
			0		0	0	block transfer mode
		BW	Byte/Word Transfer
			0	= word transfer
			1	= byte transfer
		SU	Update PTSSRC
			0	=	reload original PTS source address after each block
					transfer is complete
			1	=	retain current PTS source address after each block transfer
					is complete
		DU	Update PTSDST
			0	=	reload original PTS destination address after each block
					transfer is complete
			1	=	retain current PTS destination address after each block
					transfer is complete
		SI	PTSSRC Autoincrement
			0	=	do not increment the contents of PTSSRC
			1	=	increment the contents of PTSSRC after each byte or word
					transfer
		DI	PTSDST Autoincrement
			0	=	do not increment the contents of PTSDST
			1	=	increment the contents of PTSDST after each byte or word
					transfer
PTSCOUNT	PTSCB + 0	Consecutive Block Transfers
		Defines the number of blocks that will be transferred during the block
		transfer routine. Each block transfer is one PTS cycle. Maximum number
		is 255.

Figure 5-13. PTS Control Block – Block Transfer Mode (Continued)

5.6.5A/D Scan Mode

In the A/D scan mode, the PTS causes the A/D converter to perform multiple conversions on one or more channels and then stores the results in a table in memory. Figure 5-14 shows the PTS control block for A/D scan mode.

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STANDARD AND PTS INTERRUPTS

PTS A/D Scan Mode Control Block

In A/D scan mode, the PTS causes the A/D converter to perform multiple conversions on one or more channels and then stores the results. The control block contains pointers to both the AD_RESULT register and a table of A/D conversion commands and results (PTSPTR1 and PTSPTR2), a control register (PTSCON), and a A/D conversion count (PTSCOUNT).

	7															0
Unused			0	0			0	0			0		0		0	0
		7														0
Unused			0	0			0	0			0		0		0	0
		15														8
PTSPTR2 (H)							Pointer 2 Value (high byte)
		7														0
PTSPTR2 (L)							Pointer 2 Value (low byte)
		15														8
PTSPTR1 (H)							Pointer 1 Value (high byte)
		7														0
PTSPTR1 (L)							Pointer 1 Value (low byte)
		7														0
PTSCON			M2	M1			M0	0			UPDT		0		1	0
		7														0
PTSCOUNT							Consecutive A/D Conversions
Register	Location								Function
PTSPTR2	PTSCB + 4		Pointer 2 Value
			This register contains the address of the A/D result register
			(AD_RESULT).
PTSPTR1	PTSCB + 2		Pointer 1 Value
			This register contains the address of the table of A/D conversion
			commands and results.
PTSCON	PTSCB + 1		PTS Control Bits
			M2:0	PTS Mode
				These bits specify the PTS mode:
				M2	M1		M0
				1	1		0	A/D Scan Mode
			UPDT	Update
				0 =	reload original PTSPTR1 value after each A/D scan
				1 =	retain current PTSPTR1 value after each A/D scan

Figure 5-14. PTS Control Block – A/D Scan Mode

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8XC196Kx, Jx, CA USER’S MANUAL

PTS A/D Scan Mode Control Block (Continued)

PTSCOUNT PTSCB + 0 Consecutive A/D Conversions

Defines the number of A/D conversions that will be completed during the A/D scan routine. Each cycle consists of the PTS transferring the A/D conversion results into the command/data table, and then loading a new command into the AD_COMMAND register. Maximum number is 255.

Figure 5-14. PTS Control Block – A/D Scan Mode (Continued)

To use the A/D scan mode, you must first set up a command/data table in memory (Table 5-7). The command/data table contains A/D commands that are interleaved with blank memory locations. The PTS stores the conversion results in these blank locations. Only the amount of available memory limits the table size; it can reside in internal or external RAM.

Table 5-7. A/D Scan Mode Command/Data Table

XXX + 0AH		A/D Result 2
XXX + 8H	Unused		A/D Command 3†
XXX + 6H		A/D Result 1
XXX + 4H	Unused		A/D Command 2
XXX + 2H		A/D Result 0††
XXX	Unused		A/D Command 1

† Write 0000H to prevent a new conversion at the end of the routine.

†† Result of the A/D conversion that initiated the PTS routine.

To initiate A/D scan mode, enable the A/D conversion complete interrupt and assign it to the PTS. Software must initiate the first conversion. When the A/D finishes the first conversion and generates an A/D conversion complete interrupt, the interrupt vectors to the PTSCB and initiates the A/D scan routine. The PTS stores the conversion results, loads a new command into AD_COMMAND, and then decrements the number in PTSCOUNT. As each additional conversion complete interrupt occurs, the PTS repeats the A/D scan cycle; it stores the conversion results, loads the next conversion command into the AD_COMMAND register, and decrements PTSCOUNT. The routine continues until PTSCOUNT decrements to zero. When this occurs, hardware clears the enable bit in the PTSSEL register, which disables PTS service, and sets the PTSSRV bit, which requests an end-of-PTS interrupt. The interrupt service routine could process the conversion results and then re-enable PTS service for the A/D conversion complete interrupt. Because the lower six bits of the AD_RESULT register contain status information, the end-of- PTS interrupt service routine could shift the results data to the right six times to leave only the conversion results in the memory locations. See AP-445, 8XC196KR Peripherals: A User’s Point of View, for application examples with code.

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STANDARD AND PTS INTERRUPTS

5.6.5.1A/D Scan Mode Cycles

Software must start the first A/D conversion. After the A/D conversion complete interrupt initiates the PTS routine, the following actions occur.

1.The PTS reads the first command, stores it in a temporary location, and increments the PTSPTR1 register twice. PTSPTR1 now points to the first blank location in the command/data table (address XXXX + 2).

2.The PTS reads the AD_RESULT register, stores the results of the first conversion into location XXXX + 2 in the command/data table, and increments the PTSPTR1 register twice. PTSPTR1 now points to XXXX + 4.

3.The PTS loads the command from the temporary location into the AD_COMMAND register. This completes the first A/D scan cycle and initiates the next A/D conversion.

4.If UPDT (PTSCON.3) is clear, the original address is reloaded into the PTSPTR1 register. The next cycle will use the same command and overwrite previous data. If UPDT is set, the updated address remains in PTSPTR1 and the next cycle will use a new command and store the conversion results at the new address.

5.PTSCOUNT is decremented and the CPU returns to regular program execution. When the next A/D conversion complete interrupt occurs, the cycle repeats. When PTSCOUNT reaches zero, hardware clears the corresponding PTSSEL bit and sets the PTSSRV bit, which requests the end-of-PTS interrupt.

5.6.5.2A/D Scan Mode Example 1

The command/data table shown in Table 5-8 sets up a series of A/D conversions, beginning with channel 7 and ending with channel 4. Each table entry is a word (two bytes). Table 5-9 shows the corresponding PTSCB.

Software starts a conversion on channel 7. Upon completion of the conversion, the A/D conversion complete interrupt initiates the A/D scan mode routine. Step 1 stores the channel 6 command in a temporary location and increments PTSPTR1 to 3002H. Step 2 stores the result of the channel 7 conversion in location 3002H and increments PTSPTR1 to 3004H. Step 3 loads the channel 6 command from the temporary location into the AD_COMMAND register to start the next con-

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