8XC196Kx, Jx, CA USER’S MANUAL

9.5CONFIGURING THE SLAVE PORT

Before you can use the slave port, you must configure the associated port 3 and port 5 pins to serve as special-function signals. (See Chapter 6, “I/O Ports,” for configuration details.)

•Configure P5.3:0 as special-function inputs.

•Configure P5.4 as a special-function open-drain or complementary output.

•Configure P3.7:0 as special-function open-drain input/outputs.

The following code example shows the port 5 configuration code.

LDB	TEMP, #EFH
STB	TEMP, P5_DIR[0]	; make P5.4/SLPINT a complementary output
		; set up all other port 5 pins as inputs
LDB	TEMP, #1FH
STB	TEMP, P5_MODE[0]	; select special function for P5.4:0
LDB	TEMP, #FFH
STB	TEMP, P5_REG[0]	; write all ones to P5_REG

The following code example shows the port 3 configuration code.

LDB	TEMP, P34_DRV[0]		; read		the current		state of P34_DRV
ANDB	TEMP,	#7FH	;	clear the		MSB of	P34_DRV
STB	TEMP,	P34_DRV[0]	;	make	Port	3 open-drain

Once you have configured the pins, you must initialize the registers. This example shows the initialization code. The remaining sections of this chapter describe the registers and explain the configuration options.

LDB TEMP, #slave_mode STB TEMP, SLP_CON[0] STB ONES_REG, P3_REG[0]

STB ZERO_REG, SLP_CMD[0] STB ZERO_REG, P3_PIN[0] LDB TEMP, SLP_STAT[0]

;0FH for standard, 1BH for shared mem mode

;initialize the slave port

;write all ones to port 3 (write sets OBF)

;clear the command register

;clear the data input register

;read the status reg (CBE, IBE, OBF=111)

9.5.1Programming the Slave Port Control Register (SLP_CON)

The SLP_CON register (Figure 9-6) selects the operating mode, enables and disables slave port operation, controls whether the master accesses the data registers or the control and status registers, and controls whether the SLPINT signal is asserted when the input buffer empty (IBE) and output buffer full (OBF) flags are set in the SLP_STAT register. Only the slave can access this register.

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		SLAVE PORT
SLP_CON	Address:	1FFBH
(8XC196Kx)	Reset State:	00H

The slave port control (SLP_CON) register is used to configure the slave port. Only the slave can access the register.

	7										0
KQ, KR		—	—		—	—		SLP	SLPL	IBEMSK	OBFMSK
	7										0
KS, KT
		—	—		—	SME		SLP	SLPL	IBEMSK	OBFMSK
Bit		Bit						Function
Number	Mnemonic
7:5	—		Reserved; always write as zeros.
4†	SME		Shared Memory Enable
			Enables slave port shared memory mode.
			1 = shared memory mode
			0 = standard slave mode
3	SLP		Slave Port Enable
			This bit enables or disables the slave port.
			1 =	enables the slave port
			0 = disables the slave port and clears the command buffer empty (CBE),
				input buffer empty (IBE), and output buffer full (OBF) flags in the
				SLP_STAT register.
2	SLPL		Slave Port Latch
			In standard slave mode only, this bit determines the source of the internal
			control signal, SLP_ADDR. When SLP_ADDR is held high, the master can
			write to the SLP_CMD register and read from the SLP_STAT register. When
			SLP_ADDR is held low, the master can write to the P3_PIN register and read
			from the P3_REG register.
			1 = SLP1 (P3.1) via master’s AD1 signal. Use with multiplexed bus.
			0 = SLPALE (P5.0) via master’s A1 signal. Use with demultiplexed bus.
			In shared memory mode, this bit has no function.
1	IBEMSK		Input Buffer Empty Mask
			Controls whether the IBE flag (in SLP_STAT) asserts the SLPINT signal.
			In shared memory mode, this bit has no effect on the SLPINT signal.
0	OBFMSK		Output Buffer Full Mask
			Controls whether the OBF flag (in SLP_STAT) asserts the SLPINT signal.
			In shared memory mode, this bit has no effect on the SLPINT signal.

† On the 8XC196KQ, KR devices this bit is reserved; always write as zero.

Figure 9-6. Slave Port Control (SLP_CON) Register

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