8XC196Kx, Jx, CA USER’S MANUAL

10.3 TIMER/COUNTER FUNCTIONAL OVERVIEW

The EPA has two 16-bit up/down timer/counters, timer 1 and timer 2, which can be clocked internally or externally. Each is called a timer if it is clocked internally and a counter if it is clocked externally. Figure 10-2 illustrates the timer/counter structure.

		T2CONTROL.2:0
		3	Timer 2
	T2CLK
	FOSC/4	Prescaler	Clock
	Quadrature Count	Module
	Timer 1 Overflow		Overflow
			OVR2
	T2DIR		Interrupt
	T2CONTROL.6		Direction
	Quadrature Direction
		T1CONTROL.2:0
		3	Timer 1
	T1CLK	Prescaler
	FOSC/4		Clock
		Module
	Quadrature Count		Overflow
			OVR1
			Interrupt
	T1DIR
	T1CONTROL.6		Direction
	Quadrature Direction
	= 8XC196Kx only
			A3129-01
		Figure 10-2. EPA Timer/Counters

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EVENT PROCESSOR ARRAY (EPA)

The timer/counters can be used as time bases for input captures, output compares, and programmed interrupts (software timers). When a counter increments from FFFEH to FFFFH or decrements from 0001H to 0000H, the counter-overflow interrupt pending bit is set. This bit can optionally cause an interrupt. The clock source, direction-control source, count direction, and resolution of the input capture or output compare are all programmable (see “ Programming the Timers” on page 10-17). The maximum count rate is one-half the internal clock rate, or F OSC/4 (where FOSC is the XTAL1 frequency, in Hz). This provides a 250 ns resolution (at 16 MHz) for an input capture or output compare.

10.3.1 Cascade Mode (Timer 2 Only)

Timer 2 can be used in cascade mode. In this mode, the timer 1 overflow output is used as the timer 2 clock input. Either the direction control bit of the timer 2 control register or the direction control assigned to timer 1 controls the count direction. This method, called cascading, can provide a slow clock for idle mode timeout control or for slow pulse-width modulation (PWM) applications (see “Generating a Low-speed PWM Output” on page 10-14).

10.3.2 Quadrature Clocking Mode

On the 8XC196Kx, both timer 1 and timer 2 can be used in quadrature clocking mode. (On the 8XC196 Jx and CA, only timer 2 supports quadrature clocking mode.) This mode uses the TxCLK and TxDIR pins as quadrature inputs, as shown in Figure 10-3. External quadrature-encoded signals (two signals at the same frequency that differ in phase by 90°) are input, and the timer increments or decrements by one count on each rising edge and each falling edge. Because the TxCLK and TxDIR inputs are sampled by the internal phase clocks, transitions must be separated by at least two state times for proper operation. The count is clocked by PH2, which is PH1 delayed by one-half period. The sequence of the signal edges and levels controls the count direction. Refer to Figure 10-4 and Table 10-4 for sequencing information.

A typical source of quadrature-encoded signals is a shaft-angle decoder, shown in Figure 10-3. Its output signals X and Y are input to TxCLK and TxDIR, which in turn output signals X_internal and Y_internal. These signals are used in Figure 10-4 and Table 10-4 to describe the direction of the shaft.

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8XC196Kx, Jx, CA USER’S MANUAL
Increment		8XC196 Device
Decrement
				PH2
X				PH1
Y
	TxCLK
	D Q	D Q	D Q	X_internal
Optical
Reader	TxDIR
	D Q	D Q	D Q	Y_internal
				A0268-02

Figure 10-3. Quadrature Mode Interface

Table 10-4. Quadrature Mode Truth Table

	State of X_internal	State of Y_internal	Count Direction
	(TxCLK)	(TxDIR)
	−	0	Increment
	↓	1	Increment
	0	↓	Increment
	1	−	Increment
	↓	0	Decrement
	−	1	Decrement
	0	−	Decrement
	1	↓	Decrement

10-8