Добавил:
Опубликованный материал нарушает ваши авторские права? Сообщите нам.
Вуз: Предмет: Файл:
8XC196Kx,8XC196Jx,87C196CA microcontroller family user's manual.1995.pdf
Скачиваний:
57
Добавлен:
23.08.2013
Размер:
3.97 Mб
Скачать

SYNCHRONOUS SERIAL I/O (SSIO) PORT

8.5PROGRAMMING THE SSIO PORT

To use the SSIO port, you must configure the port pins to serve as special-function signals, then set up the SSIO channels.

8.5.1Configuring the SSIO Port Pins

Before you can use the SSIO port, you must configure the necessary port 6 pins to serve as their special-function signals. Handshaking mode requires that both the master and slave SCx pins be configured as open-drain outputs. (This configuration requires external pull-up resistors.) Table 8-1 on page 8-2 lists the pins associated with the SSIO port, and Table 8-2 lists the port configuration registers. See Chapter 6 for configuration details.

8.5.2Programming the Baud Rate and Enabling the Baud-rate Generator

The SSIO_BAUD register (Figure 8-5 on page 8-10) defines the baud rate and enables the baudrate generator. This register acts as a control register during write operations and as a downcounter monitor during read operations. The baud-rate generator provides an internal clock to the transceiver channels. The frequency ranges from FOSC/8 to FOSC/1024. With a 16-MHz oscillator frequency, this corresponds to a range from a maximum of 2.0 MHz to a minimum of 15.625 kHz. Table 8-3 lists SSIO_BAUD values for common baud rates.

Table 8-3. Common SSIO_BAUD Values at 16 MHz

Baud Rate

SSIO_BAUD Value

(Maximum) 2.0 MHz

80H

100.0 kHz

93H

64.52 kHz

9DH

50.0 kHz

A7H

25.0 kHz

CFH

(Minimum) 15.625 kHz

FFH

Bit 7 must be set to enable the baud-rate generator.

8-9

8XC196Kx, Jx, CA USER’S MANUAL

SSIO_BAUD

Address:

1FB4H

 

Reset State:

XXH

The synchronous serial port baud (SSIO_BAUD) register enables and disables the baud-rate generator and selects the SSIO baud rate. During read operations, SSIO_BAUD serves as the downcounter monitor. The down-counter is decremented once every four state times when the baud-rate generator is enabled.

7

 

 

 

 

 

 

 

 

 

 

 

 

0

BE

BV6

 

BV5

 

BV4

 

BV3

 

BV2

 

BV1

 

BV0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

Bit

 

 

 

 

Function

 

 

 

Number

Mnemonic

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

BE

Baud-rate Generator Enable

 

 

 

 

 

 

 

 

This bit enables and disables the baud-rate generator.

 

 

 

 

For write operations:

 

 

 

 

 

 

 

 

 

 

0 = disable the baud-rate generator and clear BV6:0

 

 

 

 

 

 

1 = enable the baud-rate generator and start the down-counter

 

 

 

 

For read operations:

 

 

 

 

 

 

 

 

 

 

0 = baud-rate generator is disabled

 

 

 

 

 

 

 

 

1 = baud-rate generator is enabled and down-counter is running

 

 

 

 

 

 

 

 

 

 

 

 

 

6:0

BV6:0

Baud Value

 

 

 

 

 

 

 

 

 

 

 

 

For write operations:

 

 

 

 

 

 

 

 

 

 

These bits represent BAUD_VALUE, an unsigned integer that

 

 

 

 

determines the baud rate. The maximum value of BAUD_VALUE is 7FH;

 

 

 

the minimum value is 0. Use the following equation to determine

 

 

 

 

BAUD_VALUE for a given baud rate.

 

 

 

 

 

 

 

 

 

 

 

 

FOSC

 

 

 

 

 

 

 

 

BAUD_VALUE = ------------------------------------- 1

 

 

 

 

 

 

 

 

 

 

Baud Rate × 8

 

 

 

 

 

 

 

 

For read operations:

 

 

 

 

 

 

 

 

 

 

These bits contain the current value of the down-counter.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 8-5. Synchronous Serial Port Baud (SSIO_BAUD) Register

8.5.3Controlling the Communications Mode and Handshaking

The SSIOx_CON register (Figure 8-6) controls the communications mode and handshaking. The two least-significant bits indicate whether an underflow or overflow has occurred and whether the channel is ready to transmit or receive.

8-10

SYNCHRONOUS SERIAL I/O (SSIO) PORT

SSIOx_CON

Address:

1FB1H, 1FB3H

x = 0–1

Reset State:

00H

 

 

The synchronous serial control x (SSIOx_CON) registers control the communications mode and handshaking. The two least-significant bits indicate whether an overflow or underflow has occurred and whether the channel is ready to transmit or receive.

7

 

 

 

 

 

 

 

 

 

 

 

 

 

0

M/S#

T/R#

 

TRT

 

THS

 

 

STE

 

ATR

 

OUF

TBS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

Bit

 

 

 

 

 

 

 

Function

 

 

Number

Mnemonic

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

M/S#

Master/Slave Select

 

 

 

 

 

 

 

 

 

Configures the channel as either master or slave.

 

 

 

 

 

0

= slave; SCx is an external clock input to SSIOx_BUF

 

 

 

 

1

= master; SCx is an output driven by the SSIO baud-rate generator

 

 

 

 

 

 

 

 

 

6

T/R#

Transmit/Receive Select

 

 

 

 

 

 

 

 

 

Configures the channel as either transmitter or receiver.

 

 

 

 

0

= receiver; SDx is an input to SSIOx_BUF

 

 

 

 

 

1

= transmitter; SDx is an output driven by the output of SSIOx_BUF

 

 

 

 

 

 

 

 

5

TRT

Transmitter/Receiver Toggle

 

 

 

 

 

 

 

 

Controls whether receiver and transmitter switch roles at the end of each

 

 

 

transfer.

 

 

 

 

 

 

 

 

 

 

 

 

0

= do not switch

 

 

 

 

 

 

 

 

 

1

= switch; toggle T/R# and clear TRT at the end of the current transfer

 

 

 

Setting TRT allows the channel configuration to change immediately on

 

 

 

transfer completions, thus avoiding possible contention on the data line.

 

 

 

 

 

 

 

 

4

THS

Transceiver Handshake Select

 

 

 

 

 

 

 

 

Enables and disables handshaking. The THS, STE, and ATR bits must

 

 

 

be set for handshaking modes.

 

 

 

 

 

 

 

 

0

= disables handshaking

 

 

 

 

 

 

 

 

 

1

= enables handshaking

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

STE

Single Transfer Enable

 

 

 

 

 

 

 

 

 

Enables and disables transfer of a single byte. Unless ATR is set, STE is

 

 

 

automatically cleared at the end of a transfer. The THS, STE, and ATR

 

 

 

bits must be set for handshaking modes.

 

 

 

 

 

0

= disable transfers

 

 

 

 

 

 

 

 

 

1

= allow transmission or reception of a single byte

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The M/S# and T/R# bits specify four possible configurations: master transmitter, master receiver, slave transmitter, or slave receiver.

Figure 8-6. Synchronous Serial Control x (SSIOx_CON) Registers

8-11

8XC196Kx, Jx, CA USER’S MANUAL

SSIOx_CON (Continued)

Address:

1FB1H, 1FB3H

x = 0–1

Reset State:

00H

 

 

The synchronous serial control x (SSIOx_CON) registers control the communications mode and handshaking. The two least-significant bits indicate whether an overflow or underflow has occurred and whether the channel is ready to transmit or receive.

7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

M/S#

T/R#

 

TRT

 

THS

 

 

STE

 

ATR

 

OUF

 

TBS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

Bit

 

 

 

 

 

 

Function

 

 

 

Number

Mnemonic

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

ATR

Automatic Transfer Re-enable

 

 

 

 

 

 

 

 

Enables and disables subsequent transfers. The THS, STE, and ATR bits

 

 

 

must be set for handshaking modes.

 

 

 

 

 

 

 

 

0

= allow automatic clearing of STE; disable subsequent transfers

 

 

 

1

= prevent automatic clearing of STE; allow transfer of next byte

 

 

 

 

 

 

 

 

 

 

 

1

OUF

Overflow/Underflow Flag

 

 

 

 

 

 

 

 

 

 

Indicates whether an overflow or underflow has occurred. An attempt to

 

 

 

access SSIOx_BUF during a byte transfer sets this bit.

 

 

 

 

For the master (M/S# = 1)

 

 

 

 

 

 

 

 

0

=

no overflow or underflow has occurred

 

 

 

 

 

 

1

= the core attempted to access SSIOx_BUF during the current transfer

 

 

 

For the slave (M/S# = 0)

 

 

 

 

 

 

 

 

 

 

0

= no overflow or underflow has occurred

 

 

 

 

 

 

1

=

the core attempted to access SSIOx_BUF during the current transfer

 

 

 

 

 

or the master attempted to clock data into or out of the slave’s

 

 

 

 

 

SSIOx_BUF before the buffer was available

 

 

 

 

 

 

 

 

 

 

 

 

 

0

TBS

Transceiver Buffer Status

 

 

 

 

 

 

 

 

 

 

Indicates the status of the channel’s SSIOx_BUF.

 

 

 

 

 

 

For the transmitter (T/R# =1)

 

 

 

 

 

 

 

 

0

=

SSIOx_BUF is full; waiting to transmit

 

 

 

 

 

 

1

= SSIOx_BUF is empty; buffer available

 

 

 

 

 

 

For the receiver (T/R# = 0)

 

 

 

 

 

 

 

 

0

= SSIOx_BUF is empty; waiting to receive

 

 

 

 

 

 

1

=

SSIOx_BUF is full; data available

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The M/S# and T/R# bits specify four possible configurations: master transmitter, master receiver, slave transmitter, or slave receiver.

Figure 8-6. Synchronous Serial Control x (SSIOx_CON) Registers (Continued)

8-12

Соседние файлы в предмете Электротехника