Programmer’s Model

See System initialization on page 3-10 for an example of the use of I and M to initialize SDRAM after power on.

3.3.2Refresh timer register

Refer to Table 3-5 which shows bit assignments for the refresh timer register.

			Table 3-5 Refresh timer register
Bits	Name	Type	Function
15:0	-	Read/write	The refresh timer register is a 16-bit read/write register
			that is programmed with the number of HCLK ticks that
			should be counted between SDRAM refresh cycles.

For example, for the common refresh period of 16μs, and a HCLK frequency of 50MHz, the following value should be programmed into it:

16 × 10– 6 × 50 × 106 = 800

The refresh timer is set to 128 by nPOR. To ensure a refresh interval of less than 16μs after reset, the minimum frequency of HCLK allowed is:

128

---------------------- = 8MHz 16 × 10– 6

The refresh register should be written to as early as possible in the system start-up procedure, and in the first few cycles if the system clock is less than 8MHz.

3.3.3Write buffer time-out register

This register is only present if a write buffer is included in the AMBA AHB interface. Refer to Table 3-6 which shows bit assignments for the write buffer time-out register.

			Table 3-6 Write buffer time-out register
Bits	Name	Type	Function
15:0	-	Read/write	The write buffer time-out register works with the
			optional merging write buffer. This 16-bit read/write
			register sets the delay time for a forced flush of the write
			buffer. This is useful to ensure, for instance, video
			display data is correctly updated.

3-8

© Copyright ARM Limited 1999. All rights reserved.

ARM DDI 0162B

Programmer’s Model

Any write to the merging write buffer loads the value in the timeout register into the time-out down counter. When the time-out counter reaches 0 the merging write buffer contents is written (flushed) to the external memory. The down counter is clocked by HCLK. Storing a value of 0 in the timeout register disables the write buffer timeout function.

3.3.4Lock registers

Normally each lock register is present only if the associated DMA port is present. Refer to Table 3-7 which shows bit assignments for each lock register.

				Table 3-7 Lock register bit assignments
	Lock	Bits	Type	Function
	register
	Port n	15:0	Read/	B = 1 corresponding virtual channel is locked to Port n.
			write	B = 0 corresponding virtual channel is not locked to Port n.

Note

The existence of a lock register is controlled by a define variable, PORTnLOCK_REG, n can have the value 0, 1, 2, or 3, which corresponds to the number of the associated port of the PrimeCell VC-SDRAM control engine.

The lock registers allow virtual channels to be locked to one or more ports. Each register is 16 bits wide, with bit 0 corresponding to channel 0, through to bit 15 corresponding to channel 15. All bits are read/write. Setting a bit in a lock register locks a channel to the corresponding port. Channels can be locked to more than one port.

When a channel or group of channels are locked to a port, only the locked channels are considered as replacement candidates in the event of a channel miss. If no channel for a particular port is locked, then all channels, which are not locked to other ports, are candidates for replacement.

More advanced, customized, systems could detect between different bus masters requesting access on the same bus (for example, with AHB) and automatically change the contents of the lock register for a particular port for each bus master. Also, software could alter the contents of the locked register during interrupt routines to ensure low interrupt latency.

ARM DDI 0162B

© Copyright ARM Limited 1999. All rights reserved.

3-9