Programmer’s Model

3.5Address mapping

The AHB port accesses external VC-SDRAM when HSELram is asserted. Table 3-8 shows the chip select address decoder truth table.

Table 3-8 Chip select address decoder truth table

HADDR[26]	HADDR[25]	nCSOut3	nCSOut2	nCSOut1	nCSOut0
0	0	1	1	1	0
0	1	1	1	0	1
1	0	1	0	1	1
1	1	0	1	1	1

Table 3-9 to Table 3-14 give AMBA address bus to the VC-SDRAM address AddrOut[13:0] mapping for various memory types. Memory type is selected by programming the T, B and V bits in configuration register 0. The mapping will only take effect if the define variable ADDRESS_MAPPING is set to 1.

Note

An * indicates the signal is not used.

** indicates the signal is fixed at logic 0, and is not used.

The HADDR prefixes have been omitted from Table 3-9 to Table 3-14.

Table 3-9 64M SDRAM(2Mx32, 4Mx16) T=0, V=0, B=1, use 12 and 13 as bank selects

AddrOut	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Row	10	11	23	22	21	20	19	18	17	16	15	14	13	12
Column	10	11	23	AP	**	24	9	8	7	6	5	4	3	2
		Table 3-10 64M SDRAM (8Mx8) T=1, V=0, B=1, use 12 and 13 as bank selects
AddrOut	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Row	12	11	23	22	21	20	19	18	17	16	15	14	13	24
Col	12	11	23	AP	**	10	9	8	7	6	5	4	3	2

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3-11

Programmer’s Model

Table 3-11 16M SDRAM (1Mx16) T=0, V=0, B=0, use 11 as bank select

	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Row	**	10*	10	11	21	20	19	18	17	16	15	14	13	12
Col	**	10*	10	AP	**	10*	9	8	7	6	5	4	3	2
					Table 3-12 16M SDRAM (2Mx8) T=1, V=0, B=0, use 11 as bank select
	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Row	**	11*	11	22	21	20	19	18	17	16	15	14	13	12
Col	**	11*	11	AP	**	10	9	8	7	6	5	4	3	2
					Table 3-13 64M VC-SDRAM (4Mx16) T=0, V=1, B=0, use 13 as bank select
	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Row	8	11	23	22	21	20	19	18	17	16	15	14	13	12
Col	8	-	-	-	-	-	-	-	7	6	5	4	3	2

Note

Segment address uses HADDR[10:9]

Table 3-14 64M VC-SDRAM (8Mx8) T=1, V=1, B=0, use 13 as bank select

	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Row	9	24	23	22	21	20	19	18	17	16	15	14	13	12
Col	9	-	-	-	-	-	-	8	7	6	5	4	3	2

Note

Segment address uses HADDR[11:10]

3-12

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ARM DDI 0162B

Programmer’s Model

3.5.1Remapping the AMBA address to the VC-SDRAM address bus

The mapping presented in the previous section should satisfy the following two constraints:

•memory selected by each chip select should be contiguous

•the bank address should be changed on the page address for SDRAM, or the segment address for virtual channel SDRAM.

3.5.2Mapping the DMA address buses

The DMA address buses are mapped onto the VC-SDRAM RAS and CAS addresses AddrOut[13:0] according to the basic mapping given in Table 3-15.

	Table 3-15 DMA address bus mapping
On-chip address	VC-SDRAM address
AddrInn[26:25]	Generates nCSOut[3:0]
AddrInn[24]	Bank Select [0] (two bank VC-SDRAM) (AddrOut[13])
	Bank Select [1] (four bank VC-SDRAM) (AddrOut[13])
AddrInn[23]	Bank Select [0] (AddrOut[12])
AddrInn[22:11]	Row Address (AddrOut[11:0)
AddrInn[10:2]	Column address (AddrOut[8:0])

In Table 3-15 AddrInn[] represents the address input to the VC-SDRAM controller from the n port requesting access.

For 16Mb SDRAM AddrInn[22] = AddrInn[23]

AddrOut[13:0] is the off chip address bus which connects to the VC-SDRAM.

In SDRAM mode (Vchannel bit in the status register = 0), using verilog type concatenation syntax.the row address (RAS address) is made up from:

AddrOut[13:0] = AddrInn[24:11]

The column (CAS address) is made up from:

AddrOut[13:0] = {AddrInn[24:23], AddrInn[23],AutoPre, l’b0, AddrIn n [10:2]}

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3-13

Programmer’s Model

Note

Signal names for each DMA port can be found by substituting the port number, 0, 1 or 2, for the symbol n.

The VC-SDRAM state machine generates the AutoPre output in the CAS address.

In Virtual channel mode (Vchannel bit in the status register = 1), using verilog type concatenation syntax the row address is made up from:

AddrOut[13:0] = AddrInn[24:11]

The CAS address is made up from:

AddrOut[13:0] = {B,Ch[3:2],AP,Ch[1:0],AddrInn[9:4],SAddrInn[3:2]}

BS1 is bank select segment 1. This signal is generated by using the command being issued to multiplex between bank select [0] (AddrInn[24]), logic 0.

AP is auto pre-charge.

SAddrInn[3:2] is AddrInn[3:2], or segment address [1:0] depending on the command being issued.

For virtual channel devices, the segment address is supplied by AddrInn[10:9], and the column address by AddrInn[8:2].

3.5.3Remapping the on-chip address bus to RAS and CAS address

The mapping of AddrInn[26:2] to AddrOut[13:0] presented in the previous section represents a basic generic mapping, and should be maintained for BusTalk verification. However, for a practical system, the mapping of the on-chip address to the off-chip address should typically satisfy the following two constraints:

•each target external memory device should appear contiguous in memory

•the bank address should be changed on the page address for SDRAM based systems, or the segment address for virtual channel SDRAM based systems.

In most systems the DMA address mapping will mimic the AHB address mapping. Figure A-1 on page A-4 shows the mapping between the AHB address and AddrIn3 lines for the various controller modes.

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ARM DDI 0162B

Programmer’s Model

Depending on the memory devices being used, the optimum DMA address mapping will change, and the user should remap the actual on-chip bus connections to the AddrInn[26:2] as appropriate. For example, mapping a DMA bus to external memory, made up of two 64Mb virtual channel SDRAMs with sixteen bit data buses, the mapping shown in Table 3-16 is suggested.

The mapping results in the 16MB of memory appearing twice in the 32MB of address space available to a device select (nCSOut[3:0]).

Table 3-16 Example mapping for two 64Mbit VC-SDRAMs

DMA address bus	On-chip address
DMAaddr[26:25]	AddrInn[26:25]
DMAaddr[24] (Not used)	AddrInn[8]
DMAaddr[23:11] (Row address)	AddrInn[23:11]
DMAaddr[10:9] (Segment address [1:0] – part of column	AddrInn[10:9]
address)
DMAaddr[8] (Bank address)	AddrInn[24]
DMAaddr[7:2] (Column address)	AddrInn[7:2]

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Programmer’s Model

3-16

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ARM DDI 0162B

Appendix A

ARM PrimeCell VC-SDRAM Controller (PL070)

Signal Descriptions

This appendix describes the signals that interface with the ARM PrimeCell

VC-SDRAM Controller (PL070). It contains the following sections:

•On-chip signals on page A-2

•Off-chip signals on page A-8.

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A-1