Chapter 3

Programmer’s Model

This chapter describes the registers of the PrimeCell VC-SDRAM Controller, and provides details of system initialization. It contains the following sections:

•About the programmer’s model on page 3-2

•Summary of PrimeCell VC-SDRAM Controller registers on page 3-3

•Register descriptions on page 3-4

•System initialization on page 3-10

•Address mapping on page 3-11.

ARM DDI 0162B

© Copyright ARM Limited 1999. All rights reserved.

3-1

Programmer’s Model

3.1About the programmer’s model

The base address of the PrimeCell VC-SDRAM Controller is fixed by the host ASIC AMBA address decoder. PrimeCell VC-SDRAM Controller registers are selected by HSELreg. Address lines HADDR[4:2] are used to select one of the registers when HSELreg is asserted. The registers are word-aligned.

External memory is accessed when HSELram is asserted. PrimeCell VC-SDRAM

Controller uses address lines HADDR[26:0] for memory transfers.

3-2

© Copyright ARM Limited 1999. All rights reserved.

ARM DDI 0162B

Programmer’s Model

3.2Summary of PrimeCell VC-SDRAM Controller registers

The PrimeCell VC-SDRAM Controller registers are shown in Table 3-1.

Table 3-1 PrimeCell VC-SDRAM register summary

	Address	Type	Width	Reset	Name	Description
				value
	VC-SDRAM Base	Read/write	26	0x01F00000	Reg0[25:0]	Configuration register 0.
	VC-SDRAM Base + 0x04	Read/write	6	Note 1	Reg1[5:0]	Configuration register 1.
	VC-SDRAM Base + 0x08	Read/write	16	0x080	Reg2[15:0]	Refresh timer register.
	VC-SDRAM Base + 0x0C	Read/write	16	0	Reg3[15:0]	Write buffer time-out register,
						see note 2.
	VC-SDRAM Base + 0x10	Read/write	16	0	Reg4[15:0]	Port 0 lock register, see note 3.
	VC-SDRAM Base + 0x14	Read/write	16	0	Reg5[15:0]	Port 1 lock register, see note 3.
	VC-SDRAM Base + 0x18	Read/write	16	0	Reg6[15:0]	Port 2 lock register, see note 3.
	VC-SDRAM Base + 0x1C	Read/write	16	0	Reg7[15:0]	Port 3 lock register, see note 3.

Note

1Reset value 0x10 if no buffers,

reset value of bit 2 is 1 if Rd buffer is present in design, reset value of bit 3 is 1 if Wr buffer is present in design.

2Register only present if write buffer is included in AHB interface.

3The existence of a lock register is controlled by a define variable PORTnLOCK_REG.

A lock register is only required when the associated DMA port is instantiated in the design.

ARM DDI 0162B

© Copyright ARM Limited 1999. All rights reserved.

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