Chapter 1

Introduction

This chapter introduces the ARM PrimeCell Virtual Channel SDRAM Controller (PL070) and contains the following section:

•About the ARM PrimeCell VC-SDRAM Controller (PL070) on page 1-2.

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1-1

Introduction

1.1About the ARM PrimeCell VC-SDRAM Controller (PL070)

The PrimeCell VC-SDRAM Controller is an Advanced Microcontroller Bus Architecture (AMBA) compliant, System-on-a-Chip (SoC) peripheral that is developed, tested and licensed by ARM.

The PrimeCell VC-SDRAM Controller interfaces VC-SDRAM and standard SDRAM to embedded SoC ASICs and ASSP.

Refer to Figure 1-1 for a simplified block diagram of the PrimeCell VC-SDRAM

Controller.

PrimeCell VC-SDRAM Controller

AMBA

AHB

3

bus

interface

Control

registers

VC-SDRAM

Off-chip

On-chip

control engine

PAD

buses

Port for

interface

VC-SDRAM

2

bus

DMA 2

Port for

1

DMA 1

Port for

0

DMA 0

Note: The ports for DMA 0, 1 and 2 are optional

Figure 1-1 PrimeCell VC-SDRAM Controller in a system

1.1.1VC-SDRAM overview

Virtual Channel Synchronous Dynamic Random Access Memory (VC-SDRAM) is a variant of SDRAM with additional SRAM-like memory. The extra memory is organized into sections known as Virtual Channels. Each Virtual Channel can hold a

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ARM DDI 0162B

Introduction

copy of a quarter of a row of data. Virtual Channels are accessed in the same way as an open SDRAM row (also known as a page). A typical VC-SDRAM has 16 Virtual Channels.

The advantage of having Virtual Channels is that they allow more address domains to be open concurrently, which reduces the average latency for a memory access, in comparison to SDRAM with no Virtual Channels.

Any Virtual channel can hold any quarter of any page (row). The Primecell Virtual Channel memory controller manages the allocation of Virtual Channels, keeping track of the memory address range of data held in each Virtual channel. Virtual Channels can be locked to bus masters, allowing software to manage Virtual Channel usage according to the needs of the system.

1.1.2General information

Figure 1-1 shows the on-chip buses interfaced to the controller via the AMBA AHB and DMA interfaces. The off-chip VC-SDRAM bus is resynchronized to the PrimeCell VC-SDRAM control engine via the pad interface. The bus interface also contains the control registers.

The bus and DMA interfaces can be altered to cater for the behavior of the PrimeCell VC-SDRAM Controller in most applications. Bus interface variants can cover different buffering strategies depending on:

•whether the ARM processor is cached or not

•logic for different prefetch strategies

•on or off-chip data bus width conversions

•system-dependent control registers. DMA variants may include:

•prefetch logic to prefetch the next portion of memory into a virtual channel when the end of a channel is reached

•different buffering strategies

•data bus width conversions.

Abstracting out the pad interface permits the most appropriate internal to external bus resynchronization strategy to be adopted.

Under most circumstances, the bus, and DMA interfaces permit enough scope for modification to tailor the PrimeCell VC-SDRAM Controller to a particular application. It is not envisaged that a user will need to modify the PrimeCell VC-SDRAM control engine.

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Introduction

1.1.3Features of the PrimeCell VC-SDRAM Controller

The following features are provided by the PrimeCell VC-SDRAM Controller:

•Compliance to the AMBA Specification (Rev 2.0) onwards for easy integration into SoC implementation.

•ARM BusTalk functional test environment used for validation.

•Supports SDRAMs and VC-SDRAMs.

•Compatible with ARM7, ARM9, and ARM10 processors.

•User-customizable Direct Memory Access (DMA) ports for system-specific, high-bandwidth, peripherals.

•Optional buffers are available in the AHB bus interface to improve system performance for uncached processors (for example, ARM7TDMI and ARM9TDMI).

•16 independently controlled virtual channels.

•Individual channels can be locked to different memory masters to ensure low latency accesses.

•Support for a data prefetch mechanism which enables data to be transferred to and from a virtual channel as a background operation.

•Four independently controlled chip selects.

•Data is transferred between the controller and the VC-SDRAM in quad word bursts.

•RTL can be compiled for a range of data bus widths. For example 32-bit AHB to 32-bit VC-SDRAM, 32-bit AHB to 16-bit VC-SDRAM.

•Three clock cycle latency from AMBA bus HSELram assertion to the issue of a VC-SDRAM command.

•Provision to allow multiplexing of the external memory interface pins (address and data) with other memory controller signals (SRAM, ROM and so on).

•Two reset domains allow VC-SDRAM contents to be preserved over a soft reset.

•Power saving modes dynamically control VC-SDRAM CKEOut[3:0] and

CLKOUT.

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ARM DDI 0162B