ARM PrimeCell VC-SDRAM Controller (PL070) Signal Descriptions

A.1 On-chip signals

The on-chip signals are described in the following sections:

•AMBA AHB signals

•DMA ports on page A-5

•Miscellaneous on page A-7.

A.1.1 AMBA AHB signals

Refer to Table A-1 for an overview of the AMBA AHB signals.

Note

Table A-1 includes all AMBA AHB signals but the PrimeCell VC-SDRAM does not support split transactions.

All signals are prefixed with the letter H, ensuring that the AMBA AHB signals are differentiated from other similarly named signals in a system design.

				Table A-1 AMBA AHB signals
	Name	Type	Source/	Description
			destination
	HCLK	Input	Clock source	This clock times all bus transfers. All
				signal timings are related to the rising
				edge of HCLK.
	HRESETn	Input	Reset	The bus reset signal is active LOW and is
			controller	used to reset the system and the bus. This
				is the only active LOW signal.
	HADDR[26:0]	Input	Master	The 32-bit system address bus.
	HTRANS[1:0]	Input	Master	Indicates the type of the current transfer,
				which can be NONSEQUENTIAL,
				SEQUENTIAL, IDLE or BUSY.
	HWRITE	Input	Master	When HIGH this signal indicates a write
				transfer and when LOW a read transfer.
	HSIZE[1:0]	Input	Master	Indicates the size of the transfer, which is
				typically byte (8-bit), halfword (16-bit) or
				word (32-bit).

A-2

© Copyright ARM Limited 1999. All rights reserved.

ARM DDI 0162B

ARM PrimeCell VC-SDRAM Controller (PL070) Signal Descriptions

Table A-1 AMBA AHB signals (continued)

	Name	Type	Source/	Description
			destination
	HBURST[2:0]	Input	Master	Indicates if the transfer forms part of a
				burst. Four, eight and sixteen beat bursts
				are supported and the burst may be either
				incrementing or wrapping.
	HWDATA[31:0]	Input	Master	The write data bus is used to transfer data
				from the master to the bus slaves during
				write operations. A minimum data bus
				width of 32 bits is recommended.
				However, this may easily be extended to
				allow for higher bandwidth operation.
	HSELreg	Input	Decoder	Selects the PrimeCell VC-SDRAM
				Controller registers. Address lines
				HADDR[4:2] are decoded to identify the
				target register.
	HSELram	Input	Decoder	Selects a memory transfer or VC-SDRAM
				command.
	HRDATA[31:0]	Output	Slave	The read data bus is used to transfer data
				from the PrimeCell VC-SDRAM
				Controller to the bus master during read
				operations.
	HREADYin	Input	Slave	When HIGH the HREADYin signal
				indicates that a transfer has finished on the
				bus. This signal may be driven LOW to
				extend a transfer.
	HREADYout	Output	Slave	When HIGH the HREADYout signal
				indicates that a transfer has finished on the
				bus. This signal may be driven LOW to
				extend a transfer.
	HRESP[1:0]	Output	Slave	The transfer response provides additional
				information on the status of a transfer.
				Only the OKAY response is returned by
				the PrimeCell VC-SDRAM Controller.

ARM DDI 0162B

© Copyright ARM Limited 1999. All rights reserved.

A-3

ARM PrimeCell VC-SDRAM Controller (PL070) Signal Descriptions

A.1.2

Address mapping

Figure A-1 shows the mapping between AHB HADDR[24:0] and AddrIn[24:2] for a

32-bit AHB.

V

T

B

Bank Address

Row Address

Column Address

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

0

0

0

0

H10

H10

H11 H21

H20

H19

H18

H17

H16

H15

H14

H13

H12

H10

H9

H8

H7

H6

H5

H4

H3

H2

0

0

1

H10

H11

H23

H22

H21

H20

H19

H18

H17

H16

H15

H14

H13

H12

H24

H9

H8

H7

H6

H5

H4

H3

H2

0

1

0

0

H11

H11 H22

H21

H20

H19

H18

H17

H16

H15

H14

H13

H12

H10

H9

H8

H7

H6

H5

H4

H3

H2

0

1

1

H12

H11

H23

H22

H21

H20

H19

H18

H17

H16

H15

H14

H13

H24

H10

H9

H8

H7

H6

H5

H4

H3

H2

Bank

Address

Row Address

Column Address

1

0

x

H8

H11 H23

H22

H21

H20

H19

H18

H17

H16

H15

H14

H13

H12

H10

H9

H8

H7

H6

H5

H4

H3

H2

1

1

x

H9

H24 H23

H22

H21

H20

H19

H18

H17

H16

H15

H14

H13

H12

H11

H10 H8

H7

H6

H5

H4

H3

H2

Figure A-1 Mapping between HADDR[24:0] and AddrIn[24:2]

A-4

© Copyright ARM Limited 1999. All rights reserved.

ARM DDI 0162B

ARM PrimeCell VC-SDRAM Controller (PL070) Signal Descriptions

In Figure A-1 HADDR has been abbreviated to H, AddrIn3 has been abbreviated to A.

V, T and B are the bits in Configuration register 0. T and B are selected from T[3:0] and B[3:0] by the value of HADDR[26:25].

To match the AHB address, a DMA port must multiplex the address lines AddrInn listed below:

AddrInn[24] : Mux between DMA address lines A10, A12, A8, A9 and logic 0.

AddrInn[23] : Mux between DMA address lines A11, A10 and A24.

AddrInn[22] : Mux between DMA address lines A23, A10 and A11.

AddrInn[21] : Mux between DMA address lines A22 and A11.

AddrInn[11] : Mux between DMA address lines A24 and A12.

AddrInn[10] : Mux between DMA address lines A24, A10 and A11.

AddrInn[9] : Mux between DMA address lines A9 and A10.

A.1.3 DMA ports

The PrimeCell VC-SDRAM Controller has four ports. One port (port 3) is used by the AMBA AHB. The three remaining ports can be used for separate DMA access paths to external VC-SDRAM. Concurrent access requests from the DMA ports are prioritized. Port 0 has the highest priority, port 3 the lowest. DMA ports share the read data bus RdData[31:0] output from the PrimeCell VC-SDRAM Controller. The remaining DMA interface signals are replicated for each port. Signal names for each DMA port can be found by substituting the port number, 0, 1 or 2, for the symbol n.

ARM DDI 0162B

© Copyright ARM Limited 1999. All rights reserved.

A-5

ARM PrimeCell VC-SDRAM Controller (PL070) Signal Descriptions

Unused DMA ports are disabled by connecting their inputs to logic 0. The DMA port signals are shown in Table A-2.

				Table A-2 DMA ports signals
	Signal	Type	Source/	Function
			destination
	RdData[31:0]	Output	DMA controller	Read data, common to DMA Ports
				0,1,2.
	DataInn[31:0]	Input	DMA controller	Write data from DMA Portn.
	AddrInn[26:2]	Input	DMA controller	Access address from DMA Portn.
	Readn	Input	DMA controller	Read request from DMA Portn.
	Writen	Input	DMA controller	Write request from DMA Portn.
	AutoPren	Input	DMA controller	Auto precharge all Portn accesses.
	Pren	Input	DMA controller	Prefetch request from DMA Portn.
	Lockn[15:0]	Input	DMA controller	Channel lock information from
				Portn lock register.
	DQMn[3:0]	Input	DMA controller	Data mask for accesses from DMA
				Portn.
	SplitProceedn	Input	DMA controller	Proceed response from DMA Portn.
	ReqNumCmdn[1:0]	Input	DMA controller	Number of times command to be
				repeated.
	XferOutn	Output	DMA controller	Data phase for DMA Portn accesses.
	EndOfXfern	Output	DMA controller	Indicates end of data phase.
	SplitEnn	Output	DMA controller	Split indication from DMA Portn.
	SplitWaitn	Output	DMA controller	Split wait for DMA Portn accesses.

Note

Signal names for each DMA port can be found by substituting the port number, 0, 1 or 2, for the symbol n.

A-6

© Copyright ARM Limited 1999. All rights reserved.

ARM DDI 0162B