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Файл:ARM PrimeCell VC-SDRAM controller technical reference manual.pdf
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- •Preface
- •About this document
- •Intended audience
- •Organization
- •Typographical conventions
- •Timing diagram conventions
- •Further reading
- •ARM publications
- •Feedback
- •Feedback on this document
- •Feedback on the ARM PrimeCell VC-SDRAM Controller
- •1 Introduction
- •1.1.2 General information
- •2 Functional Overview
- •2.1.2 AHB bus interface
- •2.1.3 Optional features
- •2.1.4 DMA ports
- •2.1.5 Pad interface
- •2.2.1 External bus
- •2.2.2 Internal bus
- •2.2.4 Locking virtual channels to DMA and bus interface ports
- •3 Programmer’s Model
- •3.1 About the programmer’s model
- •3.3 Register descriptions
- •3.3.1 Configuration registers
- •3.3.2 Refresh timer register
- •3.3.4 Lock registers
- •3.4 System initialization
- •3.5 Address mapping
- •3.5.2 Mapping the DMA address buses
- •A.1 On-chip signals
- •A.1.1 AMBA AHB signals
- •A.1.3 DMA ports
- •A.1.4 Miscellaneous
- •A.2 Off-chip signals
- •A.2.1 VC-SDRAM memory interface signals
ARM PrimeCell VC-SDRAM Controller (PL070) Signal Descriptions
A.1.4 Miscellaneous
Miscellaneous signals are shown in Table A-3.
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Table A-3 Miscellaneous signals |
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Signal |
Type |
Source/ |
Function |
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destination |
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nPOR |
Input |
Reset controller |
Power on reset (active low). |
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SREFReq |
Input |
Power manager |
Self-refresh request. |
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SREFAck |
Output |
Power |
Self-refresh acknowledgement. |
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manager |
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ScanEnable |
Input |
Test controller |
Place holder for ScanEnable signal. |
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ARM DDI 0162B |
© Copyright ARM Limited 1999. All rights reserved. |
A-7 |
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