- •INTRODUCTION TO ASICs
- •1.1 Types of ASICs
- •1.2 Design Flow
- •1.3 Case Study
- •1.4 Economics of ASICs
- •1.5 ASIC Cell Libraries
- •1.6 Summary
- •1.7 Problems
- •1.8 Bibliography
- •1.9 References
- •CMOS LOGIC
- •2.12 References
- •2.1 CMOS Transistors
- •2.2 The CMOS Process
- •2.3 CMOS Design Rules
- •2.4 Combinational Logic Cells
- •2.5 Sequential Logic Cells
- •2.6 Datapath Logic Cells
- •2.7 I/O Cells
- •2.8 Cell Compilers
- •2.9 Summary
- •2.10 Problems
- •2.11 Bibliography
- •ASIC LIBRARY DESIGN
- •3.1 Transistors as Resistors
- •3.3 Logical Effort
- •3.4 Library-Cell Design
- •3.5 Library Architecture
- •3.6 Gate-Array Design
- •3.7 Standard-Cell Design
- •3.8 Datapath-Cell Design
- •3.9 Summary
- •3.10 Problems
- •3.11 Bibliography
- •3.12 References
- •PROGRAMMABLE ASICs
- •4.1 The Antifuse
- •4.2 Static RAM
- •4.4 Practical Issues
- •4.5 Specifications
- •4.6 PREP Benchmarks
- •4.7 FPGA Economics
- •4.8 Summary
- •4.9 Problems
- •4.10 Bibliography
- •4.11 References
- •5.1 Actel ACT
- •5.2 Xilinx LCA
- •5.3 Altera FLEX
- •5.4 Altera MAX
- •5.5 Summary
- •5.6 Problems
- •5.7 Bibliography
- •5.8 References
- •6.1 DC Output
- •6.2 AC Output
- •6.3 DC Input
- •6.4 AC Input
- •6.5 Clock Input
- •6.6 Power Input
- •6.7 Xilinx I/O Block
- •6.8 Other I/O Cells
- •6.9 Summary
- •6.10 Problems
- •6.11 Bibliography
- •6.12 References
- •7.1 Actel ACT
- •7.2 Xilinx LCA
- •7.3 Xilinx EPLD
- •7.4 Altera MAX 5000 and 7000
- •7.5 Altera MAX 9000
- •7.6 Altera FLEX
- •7.7 Summary
- •7.8 Problems
- •7.9 Bibliography
- •7.10 References
- •8.1 Design Systems
- •8.2 Logic Synthesis
- •8.3 The Halfgate ASIC
- •8.3.4 Comparison
- •8.4 Summary
- •8.5 Problems
- •8.6 Bibliography
- •8.7 References
- •9.1 Schematic Entry
- •9.3 PLA Tools
- •9.4 EDIF
- •9.5 CFI Design Representation
- •9.6 Summary
- •9.7 Problems
- •9.8 Bibliography
- •9.9 References
- •VHDL
- •10.1 A Counter
- •10.2 A 4-bit Multiplier
- •10.3 Syntax and Semantics of VHDL
- •10.5 Entities and Architectures
- •10.6 Packages and Libraries
- •10.7 Interface Declarations
- •10.8 Type Declarations
- •10.9 Other Declarations
- •10.10 Sequential Statements
- •10.11 Operators
- •10.12 Arithmetic
- •10.13 Concurrent Statements
- •10.14 Execution
- •10.15 Configurations and Specifications
- •10.16 An Engine Controller
- •10.17 Summary
- •10.18 Problems
- •10.19 Bibliography
- •10.20 References
- •IEEE Language Reference Manual project
- •VERILOG HDL
- •11.1 A Counter
- •11.2 Basics of the Verilog Language
- •11.3 Operators
- •11.4 Hierarchy
- •11.5 Procedures and Assignments
- •11.6 Timing Controls and Delay
- •11.7 Tasks and Functions
- •11.8 Control Statements
- •11.9 Logic-Gate Modeling
- •11.10 Modeling Delay
- •11.11 Altering Parameters
- •11.12 A Viterbi Decoder
- •11.13 Other Verilog Features
- •11.14 Summary
- •11.15 Problems
- •11.16 Bibliography
- •11.17 References
- •12.2 A Comparator/MUX
- •12.3 Inside a Logic Synthesizer
- •12.6 VHDL and Logic Synthesis
- •12.8 Memory Synthesis
- •12.9 The Multiplier
- •12.10 The Engine Controller
- •12.13 Summary
- •12.14 Problems
- •12.15 Bibliography
- •12.16 References
- •SIMULATION
- •13.1 Types of Simulation
- •13.3 Logic Systems
- •13.4 How Logic Simulation
- •13.5 Cell Models
- •13.6 Delay Models
- •13.7 Static Timing Analysis
- •13.8 Formal Verification
- •13.9 Switch-Level Simulation
- •13.11 Summary
- •13.12 Problems
- •13.13 Bibliography
- •13.14 References
- •TEST
- •14.1 The Importance of Test
- •14.2 Boundary-Scan Test
- •14.3 Faults
- •14.4 Fault Simulation
- •14.6 Scan Test
- •14.7 Built-in Self-test
- •14.8 A Simple Test Example
- •14.10 Summary
- •14.11 Problems
- •14.12 Bibliography
- •14.13 References
- •15.1 Physical Design
- •15.3 System Partitioning
- •15.4 Estimating ASIC Size
- •15.5 Power Dissipation
- •15.6 FPGA Partitioning
- •15.7 Partitioning Methods
- •15.8 Summary
- •15.9 Problems
- •15.10 Bibliography
- •15.11 References
- •16.1 Floorplanning
- •16.2 Placement
- •16.3 Physical Design Flow
- •16.4 Information Formats
- •16.5 Summary
- •16.6 Problems
- •16.7 Bibliography
- •16.8 References
- •ROUTING
- •17.1 Global Routing
- •17.2 Detailed Routing
- •17.3 Special Routing
- •17.5 Summary
- •17.6 Problems
- •17.7 Bibliography
- •17.8 References
- •A.2 VHDL Syntax
- •A.3 BNF Index
- •A.5 References
- •B.2 Verilog HDL Syntax
- •B.3 BNF Index
- •B.4 Verilog HDL LRM
- •B.5 Bibliography
- •B.6 References
9.8 Bibliography
The data books from AMD, Atmel, and other PLD manufacturers are excellent sources of tutorials, examples, and information on PLD design. The EDIF tutorials produced by the EIA [ EDIF, 1988, 1989] are hard to find, but there are few other texts or sources that explain EDIF. EDIF does have a World Wide Web site at http://www.edif.org . The EDIF Technical Centre at the University of Manchester ( http://www.cs.man.ac.uk/cad , I shall refer to this as ~EDIF ) serves as a resource center for EDIF, including the formal information models of the EDIF language in EXPRESS format and the BNF definitions of the language syntax. There is a hypertext version of an EDIF 3 0 0 schematic file with hypertext links at ~EDIF/EDIFTechnicalCenter/software . CFI has a home page and links to other sites at http://www.cfi.org .
PALASM4 v1.5 is available as freeware from AMD at ftp://ftp.amd.com/pub/pld/software/palasm . The Data I/O home page at http://www.data-io.com is devoted mainly to Synario. The Viewlogic home page is http://www.viewlogic.com . Capilano Computing has a Web page at http://www.capilano.com with DesignWorks and MacABEL software. Protel ( http://www.protel.com/download.htm ) has Windows-based schematic-entry tools for FPGAs and a CUPL demonstration package. Logical Devices has a site at http://www.logicaldevices.com . Atmel has several demonstration and code examples for ABEL and CUPL at ftp://www.atmel.com/pub/atmel .
9.9 References
Page numbers in brackets after a reference indicate its location in the chapter body.
CFI Standards for Electronic Design Automation Release 1.0. 1992. CFI published a four-volume set in 1992, ISBN 1-882750-00-4 (set). The first volume, ISBN 1-882750-01-2, is approximately 300 pages and contains a brief introduction (approximately 10 pages) and the Electrical Connectivity model. Unfortunately two of the volumes were labeled as volume three. The (first) third volume is the Tool Encapsulation Specification, ISBN 1-882750-03-09 (approximately 100 pages). The (second) third volume, ISBN 1-882750-02-0, covers the Inter-Tool Communication Programming Interface (approximately 150 pages). The fourth volume, ISBN 1-882750-04-7, is approximately 100 pages long and covers the Computing Environment Services requirement [ reference location ].
EDIF is maintained by the EIA, EIA Standards Sales Office, 2001 Pennsylvania Ave., N.W., Washington, DC 20006, (202) 457-4966 [ reference location ]:
EDIF Steering Committee. 1988. EDIF Reference Manual Version 2.0.0. Washington, DC: Electronic Industries Association. ISBN 0-7908-0000-4.
EDIF Steering Committee. 1988. Introduction to EDIF. Washington, DC: Electronic Industries Association. ISBN 0-7908-0001-2.
EDIF Steering Committee. 1989. EDIF Connectivity. Washington, DC: Electronic Industries Association. ISBN 0-7908-0002-0.
EDIF Schematic Technical Subcommittee. 1989. Using EDIF 2.0.0 for Schematic Transfer. Washington, DC: Electronic Industries Association.
EXPRESS Language Reference Manual. ISO TC184/SC4/WG5 Document N14, March 29, 1991 [ reference location ].