- •INTRODUCTION TO ASICs
- •1.1 Types of ASICs
- •1.2 Design Flow
- •1.3 Case Study
- •1.4 Economics of ASICs
- •1.5 ASIC Cell Libraries
- •1.6 Summary
- •1.7 Problems
- •1.8 Bibliography
- •1.9 References
- •CMOS LOGIC
- •2.12 References
- •2.1 CMOS Transistors
- •2.2 The CMOS Process
- •2.3 CMOS Design Rules
- •2.4 Combinational Logic Cells
- •2.5 Sequential Logic Cells
- •2.6 Datapath Logic Cells
- •2.7 I/O Cells
- •2.8 Cell Compilers
- •2.9 Summary
- •2.10 Problems
- •2.11 Bibliography
- •ASIC LIBRARY DESIGN
- •3.1 Transistors as Resistors
- •3.3 Logical Effort
- •3.4 Library-Cell Design
- •3.5 Library Architecture
- •3.6 Gate-Array Design
- •3.7 Standard-Cell Design
- •3.8 Datapath-Cell Design
- •3.9 Summary
- •3.10 Problems
- •3.11 Bibliography
- •3.12 References
- •PROGRAMMABLE ASICs
- •4.1 The Antifuse
- •4.2 Static RAM
- •4.4 Practical Issues
- •4.5 Specifications
- •4.6 PREP Benchmarks
- •4.7 FPGA Economics
- •4.8 Summary
- •4.9 Problems
- •4.10 Bibliography
- •4.11 References
- •5.1 Actel ACT
- •5.2 Xilinx LCA
- •5.3 Altera FLEX
- •5.4 Altera MAX
- •5.5 Summary
- •5.6 Problems
- •5.7 Bibliography
- •5.8 References
- •6.1 DC Output
- •6.2 AC Output
- •6.3 DC Input
- •6.4 AC Input
- •6.5 Clock Input
- •6.6 Power Input
- •6.7 Xilinx I/O Block
- •6.8 Other I/O Cells
- •6.9 Summary
- •6.10 Problems
- •6.11 Bibliography
- •6.12 References
- •7.1 Actel ACT
- •7.2 Xilinx LCA
- •7.3 Xilinx EPLD
- •7.4 Altera MAX 5000 and 7000
- •7.5 Altera MAX 9000
- •7.6 Altera FLEX
- •7.7 Summary
- •7.8 Problems
- •7.9 Bibliography
- •7.10 References
- •8.1 Design Systems
- •8.2 Logic Synthesis
- •8.3 The Halfgate ASIC
- •8.3.4 Comparison
- •8.4 Summary
- •8.5 Problems
- •8.6 Bibliography
- •8.7 References
- •9.1 Schematic Entry
- •9.3 PLA Tools
- •9.4 EDIF
- •9.5 CFI Design Representation
- •9.6 Summary
- •9.7 Problems
- •9.8 Bibliography
- •9.9 References
- •VHDL
- •10.1 A Counter
- •10.2 A 4-bit Multiplier
- •10.3 Syntax and Semantics of VHDL
- •10.5 Entities and Architectures
- •10.6 Packages and Libraries
- •10.7 Interface Declarations
- •10.8 Type Declarations
- •10.9 Other Declarations
- •10.10 Sequential Statements
- •10.11 Operators
- •10.12 Arithmetic
- •10.13 Concurrent Statements
- •10.14 Execution
- •10.15 Configurations and Specifications
- •10.16 An Engine Controller
- •10.17 Summary
- •10.18 Problems
- •10.19 Bibliography
- •10.20 References
- •IEEE Language Reference Manual project
- •VERILOG HDL
- •11.1 A Counter
- •11.2 Basics of the Verilog Language
- •11.3 Operators
- •11.4 Hierarchy
- •11.5 Procedures and Assignments
- •11.6 Timing Controls and Delay
- •11.7 Tasks and Functions
- •11.8 Control Statements
- •11.9 Logic-Gate Modeling
- •11.10 Modeling Delay
- •11.11 Altering Parameters
- •11.12 A Viterbi Decoder
- •11.13 Other Verilog Features
- •11.14 Summary
- •11.15 Problems
- •11.16 Bibliography
- •11.17 References
- •12.2 A Comparator/MUX
- •12.3 Inside a Logic Synthesizer
- •12.6 VHDL and Logic Synthesis
- •12.8 Memory Synthesis
- •12.9 The Multiplier
- •12.10 The Engine Controller
- •12.13 Summary
- •12.14 Problems
- •12.15 Bibliography
- •12.16 References
- •SIMULATION
- •13.1 Types of Simulation
- •13.3 Logic Systems
- •13.4 How Logic Simulation
- •13.5 Cell Models
- •13.6 Delay Models
- •13.7 Static Timing Analysis
- •13.8 Formal Verification
- •13.9 Switch-Level Simulation
- •13.11 Summary
- •13.12 Problems
- •13.13 Bibliography
- •13.14 References
- •TEST
- •14.1 The Importance of Test
- •14.2 Boundary-Scan Test
- •14.3 Faults
- •14.4 Fault Simulation
- •14.6 Scan Test
- •14.7 Built-in Self-test
- •14.8 A Simple Test Example
- •14.10 Summary
- •14.11 Problems
- •14.12 Bibliography
- •14.13 References
- •15.1 Physical Design
- •15.3 System Partitioning
- •15.4 Estimating ASIC Size
- •15.5 Power Dissipation
- •15.6 FPGA Partitioning
- •15.7 Partitioning Methods
- •15.8 Summary
- •15.9 Problems
- •15.10 Bibliography
- •15.11 References
- •16.1 Floorplanning
- •16.2 Placement
- •16.3 Physical Design Flow
- •16.4 Information Formats
- •16.5 Summary
- •16.6 Problems
- •16.7 Bibliography
- •16.8 References
- •ROUTING
- •17.1 Global Routing
- •17.2 Detailed Routing
- •17.3 Special Routing
- •17.5 Summary
- •17.6 Problems
- •17.7 Bibliography
- •17.8 References
- •A.2 VHDL Syntax
- •A.3 BNF Index
- •A.5 References
- •B.2 Verilog HDL Syntax
- •B.3 BNF Index
- •B.4 Verilog HDL LRM
- •B.5 Bibliography
- •B.6 References
13.13 Bibliography
Capilano Computing produces books (including software) that explain its schematic editor and logic simulators, LogicWorks and DesignWorks, for PC and Macintosh platforms [ 1995], as well as its Verilog interface [1997]. The book by Ciccarelli [1995] includes a circuit simulator, BreadBoard, with a schematic-entry program.
Miczo [ 1994] covers digital simulation in general. Arora [ 1993] covers MOS models in detail. Carey et al. [1996] cover the mathematical aspects of circuit and device modeling. Cheng and Agrawal [ 1989] cover vector generation from the perspective of testing. Hëorbst s edited book contains papers on simulation [ 1986]. Hill and Coelho [ 1987] cover mixed-level or multilevel simulation. Tuinenga [ 1988], Banzhaf [ 1989], Morris [1991], Fenical [1992], Conant [1993], Nilsson and Riedel [1993], Kielkowski [ 1994], and Lamey [1995] are all introductory books on simulation using the SPICE or PSpice. The book by Al-Hashimi [1995] on PSpice covers both digital and analog simulation. Massobrio and Antognetti [ 1993] cover the internal details of the SPICE and PSpice models. Meta Software s HSPICE User Manual is very detailed and an essential companion for serious users of any flavor of the SPICE [ 1996]. McCalla [ 1988] covers the mathematical principles of circuit simulation. Ogrodzki [ 1994] covers simulation algorithms. Pillage et al. [ 1994] cover newer circuit and system simulation methods as alternatives to the SPICE including asymptotic waveform evaluation ( AWE ). Rao et al. [ 1989] cover switch-level simulation. White and Sangiovanni-Vincentelli [ 1987] cover waveform relaxation simulation. Zukowski [ 1986] is an advanced text on bounding approach to simulation. Divekar [1988] covers device modeling. Fjeldly, Ytterdal, and Shur [1997] cover device modeling and simulation. Two books by Tsividis cover device modeling: the first [ 1987] is an advanced treatment of the MOS transistor; the second [ 1996] includes an introduction to the problems of device modeling.
13.14 References
Al-Hashimi, B. 1995. The Art of Simulation Using PSpice: Analog and Digital . Boca Raton, FL: CRC Press, 249 p. ISBN 0849378958. TK454.A454.
Arora, N. 1993. MOSFET Models for VLSI Circuit Simulation: Theory and Practice. New York: Springer-Verlag, 605 p. ISBN 321182395-6, ISBN 0-387-82395-6. TK7871.95.A76.
Banzhaf, W. 1989. Computer-Aided Circuit Analysis Using SPICE. Englewood Cliffs, NJ: Prentice-Hall. ISBN 0131625799. TK454.B33.
Capilano Computing. 1995. LogicWorks 3.0 for Windows and the Macintosh. Menlo Park, CA: Addison-Wesley, 454 p. ISBN 0-8053-1319-2. TK7874.65.L65.
Capilano Computing. 1997. LogicWorks Verilog Modeler: Interactive Circuit Simulation Software for Windows and Macintosh. Menlo Park, CA: Capilano Computing, 102 p. ISBN 0201895854. TK7888.4.L64.
Carey, G. F., et al. 1996. Circuit, Device, and Process Simulation: Mathematical and Numerical Aspects. New York: Wiley, 425 p. ISBN 0471960195. TK7867.C4973. 31 pages of references.
Cheng, K.-T., and V. D. Agrawal. 1989. Unified Methods for VLSI Simulation and Test Generation. Norwell, MA: Kluwer, 148 p. ISBN 0-7923-9025-3. TK7874.C525. 377 references. The first three chapters give a good introduction to fault simulation and test-vector generation.
Ciccarelli, F. A. 1995. Circuit Modeling: Exercises and Software. 3rd ed. Englewood Cliffs: Prentice-Hall, 190 p. ISBN 0023224738. TK454.C59. Includes BreadBoard, an IBM-PC compatible circuit analysis computer program.
Conant, R. 1993. Engineering Circuit Analysis with PSpice and Probe: Macintosh Version. New York: McGraw-Hill, 176 p. ISBN 0079116795. TK454.C674.
Divekar, D. 1988. FET Modeling for Circuit Simulation. Boston: Kluwer, 183 p. ISBN 0898382645. TK7871.95.D58. 12 pages of references.
Fenical, L. H. 1992. PSpice: A Tutorial. Englewood Cliffs, NJ: Prentice-Hall, 344 p. ISBN 0136811493. TK454.F46.
Fjeldly, T. A., T. Ytterdal, and M. Shur. 1997. Introduction to Device Modeling
and Circuit Simulation. New York: Wiley, ISBN 0471157783. TK7871.85.F593.
Hëorbst, E. (Ed.). 1986. Logic Design and Simulation. New York: Elsevier Science. ISBN 0-444-87892-0. TK7868.L6L624.
Hill, D. D., and D. R. Coelho. 1987. Multi-Level Simulation for VLSI Design. Boston: Kluwer, 206 p. ISBN 0-89838-184-3. TK7874.H525.
IEEE 1076.4-1995. IEEE Standard VITAL Application-Specific Integrated Circuit (ASIC) Modeling Specification. 96p. ISBN 1-55937-691-0. IEEE Ref. SH94382-NYF. The Institute of Electrical and Electronics Engineers. Available from The IEEE, 345 East 47th Street, New York, NY 10017 USA. [cited on reference location of this chapter]
Kielkowski, R. M. 1994. Inside SPICE: Overcoming the Obstacles of Circuit Simulation. New York: McGraw-Hill, 188 p. ISBN 0-07-911525-X. TK454.K48.
Lamey, R. 1995. The Illustrated Guide to PSpice. Albany, NY: Delmar, 219 p. ISBN 0827365241. TK454.L35.
Massobrio, G., and P. Antognetti. 1993. Semiconductor Device Modeling with SPICE. New York: McGraw-Hill, 479 p. ISBN 0-07-002469-3. TK7871.85.S4454. Contains a more detailed analysis of the SPICE models than other introductory texts.
McCalla, W. J. 1988. Fundamentals of Computer-Aided Circuit Simulation. Boston: Kluwer, 175 p. ISBN 0-89838-248-3. TK7874.M355.
Meta Software. 1996. HSPICE User s Manual. No catalog information. Available from Customer Service, 1300 White Oaks Road, Campbell, CA 95008, cs@metasw.com . This is a three-volume paperback set that is available separately from the HSPICE program. Volume I, Simulation and Analysis, explains the operation of the HSPICE program. Volume II, Elements and Device Models, contains a comprehensive description of all device models used in HSPICE. Volume III, Analysis and Methods, details input control, types of analysis, output format, optimization, filter and system design, statistical and worst-case analysis, characterization, behavioral applications, and signal integrity (packaging). [cited on reference location , reference location , reference location , reference location of this chapter]
Miczo, A. 1994. Digital Logic Testing and Simulation. New York: Harper & Row, 414 p. ISBN 0-06-044444-4. TK7868.D5M49.
Morris, J. F. 1991. Introduction to PSpice with Student Exercise Disk. Boston: Houghton Mifflin, 145 p. ISBN 0395571073. TK454.M66. To accompany text, Basic Circuit Analysis, Cunningham and Stuller.
Nilsson, J. W., and S. A. Riedel. 1993. Introduction to PSpice. Reading, MA: Addison-Wesley, 154 p. ISBN 0201513188. TK454.N54. This is a supplement to the book Electric Circuits, fourth edition, but is also very useful as a stand-alone
text.
Ogrodzki, J. 1994. Circuit Simulation Methods and Algorithms. Boca Raton, FL: CRC Press, 465 p. ISBN 0-8493-7894-X. TK7867.O33.
Pillage, L., et al. 1994. Electronic Circuit and System Simulation Methods. New York: McGraw-Hill, 392 p. ISBN 0-07-050169-6. TK7874.P52.
Rao, V. B., et al. 1989. Switch-Level Timing Simulation of MOS VLSI Circuits. Boston: Kluwer, 209 p. ISBN 0-89838-302-1. TK7874.S87. Fairly mathematical treatment of network partitioning techniques for switch-level simulators.
Tsividis, Y. P. 1987. Operation and Modeling of the MOS Transistor. New York: McGraw-Hill, 505 p. ISBN 0-07-065381-X. TK7871.99.M44.T77. [cited on reference location of this chapter]
Tsividis, Y. P. 1996. Mixed Analog-Digital VLSI Devices and Technology: An Introduction. New York: McGraw-Hill, 284 p. ISBN 0-07-065402-6. TK7874.75.T78.
Tuinenga, P. W. 1988. SPICE: A Guide to Circuit Simulation and Analysis using PSpice. Englewood Cliffs, NJ: Prentice-Hall, 200 p. ISBN 0-13-834607-0. TK454.T85.
White, J. K., and A. Sangiovanni-Vincentelli. 1987. Relaxation Techniques for the Simulation of VLSI Circuits. Boston: Kluwer, 202 p. ISBN 0-89838-186-X. TK7874.W48. Contents: Introduction; The Circuit Simulation Problem; Numerical Techniques; Waveform Relaxation; The Implementation of WR.
Zukowski, C. A. 1986. The Bounding Approach to VLSI Circuit Simulation. Norwell, MA: Kluwer, 220 p. ISBN 0-89838-176-2. TK7874.Z85. Based on an MIT Ph.D. thesis. Uses bounds on transient response of RC-networks to simplify circuit simulation. Contents: Introduction, VLSI Circuit Simulation; Simulation with Bounds; The VLSI Circuit Model; Bound Relaxation; Algorithms and Experimental Results; Conclusion.