- •Features
- •Pin Configurations
- •Disclaimer
- •Overview
- •Block Diagram
- •AT90S8535 Compatibility
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •RESET
- •XTAL1
- •XTAL2
- •AVCC
- •AREF
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •I/O Memory
- •Clock Systems and their Distribution
- •CPU Clock – clkCPU
- •I/O Clock – clkI/O
- •Flash Clock – clkFLASH
- •ADC Clock – clkADC
- •Clock Sources
- •Default Clock Source
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Timer/Counter Oscillator
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Standby Mode
- •Extended Standby Mode
- •Analog-to-Digital Converter
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watchdog Timer
- •Safety Level 0
- •Safety Level 1
- •Safety Level 2
- •Interrupts
- •I/O-Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Unconnected pins
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions Of Port B
- •Alternate Functions of Port C
- •Alternate Functions of Port D
- •Port A Data Register – PORTA
- •Port B Data Register – PORTB
- •Port C Data Register – PORTC
- •Port D Data Register – PORTD
- •External Interrupts
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •16-bit Timer/Counter1
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Trigger Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •8-bit Timer/Counter2 with PWM and Asynchronous Operation
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Timer/Counter Prescaler
- •Slave Mode
- •Master Mode
- •SPI Control Register – SPCR
- •SPI Status Register – SPSR
- •SPI Data Register – SPDR
- •Data Modes
- •USART
- •Overview
- •AVR USART vs. AVR UART – Compatibility
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Sending Frames with 5 to 8 Data Bits
- •Sending Frames with 9 Data Bits
- •Parity Generator
- •Disabling the Transmitter
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Write Access
- •Read Access
- •Two-wire Serial Interface
- •Features
- •TWI Terminology
- •Electrical Interconnection
- •Transferring Bits
- •START and STOP Conditions
- •Address Packet Format
- •Data Packet Format
- •Overview of the TWI Module
- •SCL and SDA Pins
- •Bit Rate Generator Unit
- •Bus Interface Unit
- •Address Match Unit
- •Control Unit
- •TWI Register Description
- •TWI Bit Rate Register – TWBR
- •TWI Control Register – TWCR
- •TWI Status Register – TWSR
- •TWI Data Register – TWDR
- •Using the TWI
- •Transmission Modes
- •Master Transmitter Mode
- •Master Receiver Mode
- •Slave Receiver Mode
- •Slave Transmitter Mode
- •Miscellaneous States
- •Analog Comparator
- •Analog Comparator Multiplexed Input
- •Features
- •Operation
- •Starting a Conversion
- •Differential Gain Channels
- •Changing Channel or Reference Selection
- •ADC Input Channels
- •ADC Voltage Reference
- •ADC Noise Canceler
- •Analog Input Circuitry
- •ADC Accuracy Definitions
- •ADC Conversion Result
- •ADLAR = 0
- •ADLAR = 1
- •Boot Loader Features
- •Application Section
- •BLS – Boot Loader Section
- •Boot Loader Lock Bits
- •Performing a Page Write
- •Using the SPM Interrupt
- •Setting the Boot Loader Lock Bits by SPM
- •Reading the Fuse and Lock Bits from Software
- •Preventing Flash Corruption
- •Simple Assembly Code Example for a Boot Loader
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •Electrical Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •Two-wire Serial Interface Characteristics
- •ADC Characteristics – Preliminary Data
- •Instruction Set Summary
- •Ordering Information(1)
- •Packaging Information
- •Data Sheet Change Log for ATmega8535
- •Changes from Rev. 2502A-06/02 to Rev. 2502B-09/02
- •Table of Contents
Pin Configurations
Figure 1. Pinout ATmega8535
(XCK/T0) PB0 |
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PA0 (ADC0) |
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(T1) PB1 |
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PA1 (ADC1) |
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(INT2/AIN0) PB2 |
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PA2 (ADC2) |
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(OC0/AIN1) PB3 |
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PA3 (ADC3) |
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(SS) |
PB4 |
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PA4 (ADC4) |
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(MOSI) PB5 |
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PA5 (ADC5) |
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(MISO) PB6 |
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PA6 (ADC6) |
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(SCK) PB7 |
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PA7 (ADC7) |
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RESET |
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AREF |
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VCC |
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GND |
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GND |
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AVCC |
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XTAL2 |
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PC7 (TOSC2) |
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XTAL1 |
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PC6 (TOSC1) |
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(RXD) PD0 |
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PC5 |
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(TXD) PD1 |
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PC4 |
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(INT0) PD2 |
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PC3 |
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(INT1) PD3 |
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PC2 |
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(OC1B) PD4 |
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PC1 (SDA) |
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(OC1A) PD5 |
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PC0 (SCL) |
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(ICP) PD6 |
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PD7 (OC2) |
(SS) |
(AIN1/OC0) |
(AIN0/INT2) |
(T1) |
(XCK/T0) |
GND |
VCC |
(ADC0) |
(ADC1) |
(ADC2) |
(ADC3) |
PB4 |
PB3 |
PB2 |
PB1 |
PB0 |
PA0 |
PA1 |
PA2 |
PA3 |
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44 |
43 |
42 |
41 |
40 |
39 |
38 |
37 |
36 |
35 |
34 |
(MOSI) PB5 |
1 |
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33 |
PA4 (ADC4) |
(MISO) PB6 |
2 |
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32 |
PA5 (ADC5) |
(SCK) PB7 |
3 |
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31 |
PA6 (ADC6) |
RESET |
4 |
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30 |
PA7 (ADC7) |
VCC |
5 |
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29 |
AREF |
GND |
6 |
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28 |
GND |
XTAL2 |
7 |
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27 |
AVCC |
XTAL1 |
8 |
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26 |
PC7 (TOSC2) |
(RXD) PD0 |
9 |
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25 |
PC6 (TOSC1) |
(TXD) PD1 |
10 |
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24 |
PC5 |
(INT0) PD2 |
11 |
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23 |
PC4 |
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12 |
13 |
14 |
15 |
16 |
17 |
18 |
19 |
20 |
21 |
22 |
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PD3 |
PD4 |
PD5 |
PD6 |
PD7 |
VCC |
GND |
PC0 |
PC1 |
PC2 |
PC3 |
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(INT1) |
(OC1B) |
(OC1A) |
(ICP) |
(OC2) |
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(SCL) |
(SDA) |
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PLCC
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(SS) |
(AIN1/OC0) |
(AIN0/INT2) |
(T1) |
(XCK/T0) |
GND |
VCC |
(ADC0) |
(ADC1) |
(ADC2) |
(ADC3) |
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PB4 |
PB3 |
PB2 |
PB1 |
PB0 |
PA0 |
PA1 |
PA2 |
PA3 |
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(MOSI) PB5 |
6 |
5 |
4 |
3 |
2 |
1 |
44 |
43 |
42 |
41 |
40 |
PA4 (ADC4) |
7 |
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39 |
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(MISO) PB6 |
8 |
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38 |
PA5 (ADC5) |
(SCK) PB7 |
9 |
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37 |
PA6 (ADC6) |
RESET |
10 |
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36 |
PA7 (ADC7) |
VCC |
11 |
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35 |
AREF |
GND |
12 |
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34 |
GND |
XTAL2 |
13 |
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33 |
AVCC |
XTAL1 |
14 |
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32 |
PC7 (TOSC2) |
(RXD) PD0 |
15 |
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31 |
PC6 (TOSC1) |
(TXD) PD1 |
16 |
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30 |
PC5 |
(INT0) PD2 |
17 |
19 |
20 |
21 |
22 |
23 |
24 |
25 |
26 |
27 |
29 |
PC4 |
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18 |
28 |
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PD3 |
PD4 |
PD5 |
PD6 |
PD7 |
VCC |
GND |
PC0 |
PC1 |
PC2 |
PC3 |
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(INT1) |
(OC1B) |
(OC1A) |
(ICP) |
(OC2) |
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(SCL) |
(SDA) |
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Disclaimer |
Typical values contained in this data sheet are based on simulations and characteriza- |
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tion of other AVR microcontrollers manufactured on the same process technology. Min |
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and Max values will be available after the device is characterized. |
2 ATmega8535(L)
2502B–AVR–09/02