- •Features
- •Pin Configurations
- •Disclaimer
- •Overview
- •Block Diagram
- •AT90S8535 Compatibility
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •RESET
- •XTAL1
- •XTAL2
- •AVCC
- •AREF
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •I/O Memory
- •Clock Systems and their Distribution
- •CPU Clock – clkCPU
- •I/O Clock – clkI/O
- •Flash Clock – clkFLASH
- •ADC Clock – clkADC
- •Clock Sources
- •Default Clock Source
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Timer/Counter Oscillator
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Standby Mode
- •Extended Standby Mode
- •Analog-to-Digital Converter
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watchdog Timer
- •Safety Level 0
- •Safety Level 1
- •Safety Level 2
- •Interrupts
- •I/O-Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Unconnected pins
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions Of Port B
- •Alternate Functions of Port C
- •Alternate Functions of Port D
- •Port A Data Register – PORTA
- •Port B Data Register – PORTB
- •Port C Data Register – PORTC
- •Port D Data Register – PORTD
- •External Interrupts
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •16-bit Timer/Counter1
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Trigger Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •8-bit Timer/Counter2 with PWM and Asynchronous Operation
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Timer/Counter Prescaler
- •Slave Mode
- •Master Mode
- •SPI Control Register – SPCR
- •SPI Status Register – SPSR
- •SPI Data Register – SPDR
- •Data Modes
- •USART
- •Overview
- •AVR USART vs. AVR UART – Compatibility
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Sending Frames with 5 to 8 Data Bits
- •Sending Frames with 9 Data Bits
- •Parity Generator
- •Disabling the Transmitter
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Write Access
- •Read Access
- •Two-wire Serial Interface
- •Features
- •TWI Terminology
- •Electrical Interconnection
- •Transferring Bits
- •START and STOP Conditions
- •Address Packet Format
- •Data Packet Format
- •Overview of the TWI Module
- •SCL and SDA Pins
- •Bit Rate Generator Unit
- •Bus Interface Unit
- •Address Match Unit
- •Control Unit
- •TWI Register Description
- •TWI Bit Rate Register – TWBR
- •TWI Control Register – TWCR
- •TWI Status Register – TWSR
- •TWI Data Register – TWDR
- •Using the TWI
- •Transmission Modes
- •Master Transmitter Mode
- •Master Receiver Mode
- •Slave Receiver Mode
- •Slave Transmitter Mode
- •Miscellaneous States
- •Analog Comparator
- •Analog Comparator Multiplexed Input
- •Features
- •Operation
- •Starting a Conversion
- •Differential Gain Channels
- •Changing Channel or Reference Selection
- •ADC Input Channels
- •ADC Voltage Reference
- •ADC Noise Canceler
- •Analog Input Circuitry
- •ADC Accuracy Definitions
- •ADC Conversion Result
- •ADLAR = 0
- •ADLAR = 1
- •Boot Loader Features
- •Application Section
- •BLS – Boot Loader Section
- •Boot Loader Lock Bits
- •Performing a Page Write
- •Using the SPM Interrupt
- •Setting the Boot Loader Lock Bits by SPM
- •Reading the Fuse and Lock Bits from Software
- •Preventing Flash Corruption
- •Simple Assembly Code Example for a Boot Loader
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •Electrical Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •Two-wire Serial Interface Characteristics
- •ADC Characteristics – Preliminary Data
- •Instruction Set Summary
- •Ordering Information(1)
- •Packaging Information
- •Data Sheet Change Log for ATmega8535
- •Changes from Rev. 2502A-06/02 to Rev. 2502B-09/02
- •Table of Contents
8-bit Timer/Counter2 with PWM and Asynchronous Operation
Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are:
•Single Channel Counter
•Clear Timer on Compare Match (Auto Reload)
•Glitch-free, Phase Correct Pulse Width Modulator (PWM)
•Frequency Generator
•10-bit Clock Prescaler
•Overflow and Compare Match Interrupt Sources (TOV2 and OCF2)
•Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock
Overview |
A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 53. For the |
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actual placement of I/O pins, refer to “Pinout ATmega8535” on page 2. CPU accessible |
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I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O |
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Register and bit locations are listed in the “8-bit Timer/Counter Register Description” on |
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page 125. |
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Figure 53. 8-bit Timer/Counter Block Diagram |
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TCCRn |
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count |
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TOVn |
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clear |
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Control Logic |
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(Int.Req.) |
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direction |
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clkTn |
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TOSC1 |
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BOTTOM |
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TOP |
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T/C |
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Prescaler |
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Oscillator |
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TOSC2 |
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Timer/Counter |
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TCNTn |
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= 0 |
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= 0xFF |
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clkI/O |
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OCn |
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(Int.Req.) |
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Waveform |
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OCn |
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Generation |
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DATABUS |
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OCRn |
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clkI/O |
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Synchronized Status Flags |
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Status Flags |
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Synchronization Unit |
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clkASY |
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ASSRn |
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Asynchronous Mode |
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Select (ASn) |
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114 ATmega8535(L)
2502B–AVR–09/02
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ATmega8535(L) |
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Registers |
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The Timer/Counter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers. |
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Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag |
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Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask |
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Register (TIMSK). TIFR and TIMSK are not shown in the figure since these registers are |
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shared by other timer units. |
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The Timer/Counter can be clocked internally, via the prescaler, or asynchronously |
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clocked from the TOSC1/2 pins, as detailed later in this section. The asynchronous |
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operation is controlled by the Asynchronous Status Register (ASSR). The Clock Select |
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logic block controls which clock source the Timer/Counter uses to increment (or decre- |
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ment) its value. The Timer/Counter is inactive when no clock source is selected. The |
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output from the Clock Select logic is referred to as the timer clock (clkT2). |
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The double buffered Output Compare Register (OCR2) is compared with the |
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Timer/Counter value at all times. The result of the compare can be used by the Wave- |
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form Generator to generate a PWM or variable frequency output on the Output Compare |
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Pin (OC2). See “Output Compare Unit” on page 116 for details. The compare match |
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event will also set the Compare Flag (OCF2) which can be used to generate an output |
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compare interrupt request. |
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Definitions |
Many register and bit references in this section are written in general form. A lower case |
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“n” replaces the Timer/Counter number, in this case 2. However, when using the register |
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or bit defines in a program, the precise form must be used (i.e., TCNT2 for accessing |
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Timer/Counter2 counter value and so on). |
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The definitions in Table 50 are also used extensively throughout this section. |
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Table 50. Definitions |
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BOTTOM |
The counter reaches the BOTTOM when it becomes zero (0x00). |
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MAX |
The counter reaches its MAXimum when it becomes 0xFF (decimal 255). |
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TOP |
The counter reaches the TOP when it becomes equal to the highest |
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value in the count sequence. The TOP value can be assigned to be the |
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fixed value 0xFF (MAX) or the value stored in the OCR2 Register. The |
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assignment is dependent on the mode of operation. |
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Timer/Counter Clock
Sources
The Timer/Counter can be clocked by an internal synchronous or an external asynchro-
nous clock source. The clock source clkT2 is by default equal to the MCU clock, clkI/O. When the AS2 bit in the ASSR Register is written to logic one, the clock source is taken
from the Timer/Counter Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see “Asynchronous Status Register – ASSR” on page 128. For details on clock sources and prescaler, see “Timer/Counter Prescaler” on page 131.
115
2502B–AVR–09/02