Electrical Characteristics

Absolute Maximum Ratings*

..................................Operating Temperature					-55°C to +125°C	*NOTICE: Stresses beyond those listed under “Absolute
						Maximum Ratings” may cause permanent dam-
Storage Temperature .....................................					-65°C to +150°C	age to the device. This is a stress rating only and
						functional operation of the device at these or
Voltage on any Pin except						other conditions beyond those indicated in the
			RESET
with respect to Ground ................................					- 1.0V to VCC+0.5V	operational sections of this specification is not
						implied. Exposure to absolute maximum rating
Voltage on	RESET	with respect to Ground			......-1.0V to +13.0V	conditions for extended periods may affect
Maximum Operating Voltage					6.0V	device reliability.
DC Current per I/O Pin ...............................................					40.0 mA
DC Current VCC and GND Pins ................................					200.0 mA

DC Characteristics TA = -40°C to 85°C, VCC = 2.7V to 5.5V (unless otherwise noted)

Symbol

Parameter

Condition

Min

Typ

Max

Units

VIL

Input Low Voltage

Except XTAL1 pin

-0.5

(1)

V

0.2 VCC

VIL1

XTAL1 pin, External

(1)

Input Low Voltage

Clock Selected

-0.5

0.1 VCC

V

VIH

Input High Voltage

Except XTAL1 and

0.6 VCC

(2)

VCC + 0.5

V

RESET

pins

VIH1

Input High Voltage

XTAL1 pin, External

0.8 VCC

(2)

VCC + 0.5

V

Clock Selected

VIH2

(2)

Input High Voltage

RESET pin

0.9 VCC

VCC + 0.4

V

Output Low Voltage(3)

I

= 20 mA, V

CC

= 5V

0.6

V

VOL

OL

(Ports A,B,C,D)

IOL = 10 mA, VCC = 3V

0.5

V

Output High Voltage(4)

I

= -20 mA, V

= 5V

4.2

V

VOH

OH

CC

(Ports A,B,C,D)

IOH = -10 mA, VCC = 3V

2.3

V

IIL

Input Leakage

VCC = 5.5V, pin low

8

µA

Current I/O Pin

(absolute value)

IIH

Input Leakage

VCC = 5.5V, pin high

8

nA

Current I/O Pin

(absolute value)

RRST

Reset Pull-up Resistor

20

100

kΩ

Rpu

I/O Pin Pull-up Resistor

20

100

kΩ

Active 4 MHz, VCC = 3V

3

mA

(ATmega8535L)

Active 8 MHz, VCC = 5V

11

mA

(ATmega8535)

Power Supply Current

ICC

Idle 4 MHz, VCC = 3V

1.5

mA

(ATmega8535L)

Idle 8 MHz, VCC = 5V

5.5

mA

(ATmega8535)

Power-down mode(5)

WDT enabled, VCC = 3V

< 1

µA

WDT disabled, VCC = 3V

< 10

µA

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2502B–AVR–09/02

ATmega8535(L)

DC Characteristics TA = -40°C to 85°C, VCC = 2.7V to 5.5V (unless otherwise noted) (Continued)

Symbol	Parameter	Condition	Min	Typ	Max	Units
VACIO	Analog Comparator	VCC = 5V			40	mV
	Input Offset Voltage	Vin = VCC/2
IACLK	Analog Comparator	VCC = 5V	-50		50	nA
	Input Leakage Current	Vin = VCC/2
tACID	Analog Comparator	VCC = 2.7V		750		ns
	Propagation Delay	VCC = 4.0V		500

Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low.

2.“Min” means the lowest value where the pin is guaranteed to be read as high.

3.Although each I/O port can sink more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed:

PDIP Package:

1] The sum of all IOL, for all ports, should not exceed 200 mA.

2] The sum of all IOL, for port A0 - A7, should not exceed 100 mA.

3] The sum of all IOL, for ports B0 - B7,C0 - C7, D0 - D7 and XTAL2, should not exceed 100 mA. TQFP Package:

1] The sum of all IOL, for all ports, should not exceed 400 mA.

2] The sum of all IOL, for ports A0 - A7, should not exceed 100 mA. 3] The sum of all IOL, for ports B0 - B3, should not exceed 100 mA. 4] The sum of all IOL, for ports B4 - B7, should not exceed 100 mA. 5] The sum of all IOL, for ports C0 - C3, should not exceed 100 mA. 6] The sum of all IOL, for ports C4 - C7, should not exceed 100 mA.

7] The sum of all IOL, for ports D0 - D3 and XTAL2, should not exceed 100 mA. 8] The sum of all IOL, for ports D4 - D7, should not exceed 100 mA.

If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition.

4.Although each I/O port can source more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed:

PDIP Package:

1] The sum of all IOH, for all ports, should not exceed 200 mA.

2] The sum of all IOH, for port A0 - A7, should not exceed 100 mA.

3] The sum of all IOH, for ports B0 - B7,C0 - C7, D0 - D7 and XTAL2, should not exceed 100 mA. TQFP Package:

1] The sum of all IOH, for all ports, should not exceed 400 mA.

2] The sum of all IOH, for ports A0 - A7, should not exceed 100 mA. 3] The sum of all IOH, for ports B0 - B3, should not exceed 100 mA. 4] The sum of all IOH, for ports B4 - B7, should not exceed 100 mA. 5] The sum of all IOH, for ports C0 - C3, should not exceed 100 mA. 6] The sum of all IOH, for ports C4 - C7, should not exceed 100 mA.

7] The sum of all IOH, for ports D0 - D3 and XTAL2, should not exceed 100 mA. 8] The sum of all IOH, for ports D4 - D7, should not exceed 100 mA

If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition.

5.Minimum VCC for Power-down is 2.5V.

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2502B–AVR–09/02

External Clock Drive

Waveforms

External Clock Drive

Figure 127. External Clock Drive Waveforms

VIH1

VIL1

Table 111. External Clock Drive

VCC = 2.7V to 5.5V

VCC = 4.5V to 5.5V

Symbol

Parameter

Min

Max

Min

Max

Units

1/tCLCL

Oscillator Frequency

0

8

0

16

MHz

tCLCL

Clock Period

125

62.5

ns

tCHCX

High Time

50

25

ns

tCLCX

Low Time

50

25

ns

tCLCH

Rise Time

1.6

0.5

µs

tCHCL

Fall Time

1.6

0.5

µs

Change in period from

∆tCLCL

one clock cycle to the

2

2

%

next

Table 112. External RC Oscillator, Typical Frequencies(1)

R [kΩ]

C [pF]

f

100

70

TBD

31.5

20

TBD

6.5

20

TBD

Note: 1.

R should be in the range 3 kΩ - 100 kΩ, and C should be at least 20 pF. The C values

given in the table includes pin capacitance. This will vary with package type.

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ATmega8535(L)

Two-wire Serial Interface Characteristics

Table 113 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega8535 Two-wire Serial Interface meets or exceeds these requirements under the noted conditions.

Timing symbols refer to Figure 128.

Table 113. Two-wire Serial Bus Requirements

Symbol

Parameter

Condition

Min

Max

Units

VIL

Input Low Voltage

-0.5

0.3 VCC

V

VIH

Input High Voltage

0.7 VCC

VCC + 0.5

V

(1)

Hysteresis of Schmitt Trigger Inputs

(2)

–

V

Vhys

0.05 VCC

(1)

Output Low Voltage

3 mA sink current

0

0.4

V

VOL

(1)

Rise Time for both SDA and SCL

20 + 0.1C

(3)(2)

300

ns

tr

b

(1)

Output Fall Time from VIHmin to VILmax

10 pF < Cb < 400 pF

(3)

(3)(2)

250

ns

tof

20 + 0.1Cb

(1)

Spikes Suppressed by Input Filter

0

50

(2)

ns

tSP

Ii

Input Current each I/O Pin

0.1VCC < Vi < 0.9VCC

-10

10

µA

C (1)

Capacitance for each I/O Pin

–

10

pF

i

f

SCL Clock Frequency

f

(4) > max(16f

SCL

, 250kHz)(5)

0

400

kHz

SCL

CK

fSCL ≤ 100 kHz

VCC – 0.4V

1000ns

Ω

----------------------------

-------------------

Rp

Value of Pull-up resistor

3mA

Cb

fSCL > 100 kHz

VCC – 0.4V

300ns

Ω

----------------------------

---------------

3mA

Cb

tHD;STA

Hold Time (Repeated) START Condition

fSCL ≤ 100 kHz

4.0

–

µs

fSCL > 100 kHz

0.6

–

µs

tLOW

Low Period of the SCL Clock

fSCL ≤ 100 kHz(6)

4.7

–

µs

fSCL > 100 kHz(7)

1.3

–

µs

tHIGH

High Period of the SCL clock

fSCL ≤ 100 kHz

4.0

–

µs

fSCL > 100 kHz

0.6

–

µs

tSU;STA

Set-up Time for a Repeated START

fSCL ≤ 100 kHz

4.7

–

µs

Condition

fSCL > 100 kHz

0.6

–

µs

tHD;DAT

Data hoLd Time

fSCL ≤ 100 kHz

0

3.45

µs

fSCL > 100 kHz

0

0.9

µs

tSU;DAT

Data Setup Time

fSCL ≤ 100 kHz

250

–

ns

fSCL > 100 kHz

100

–

ns

tSU;STO

Setup Time for STOP Condition

fSCL ≤ 100 kHz

4.0

–

µs

fSCL > 100 kHz

0.6

–

µs

tBUF

Bus Free Time between a STOP and START

fSCL ≤ 100 kHz

4.7

–

µs

Condition

fSCL > 100 kHz

1.3

–

µs

Notes: 1. In ATmega8535, this parameter is characterized and not 100% tested.

2.Required only for fSCL > 100 kHz.

3.Cb = capacitance of one bus line in pF.

4.fCK = CPU clock frequency.

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2502B–AVR–09/02

5.This requirement applies to all ATmega8535 Two-wire Serial Interface operation. Other devices connected to the Two-wire Serial Bus need only obey the general fSCL requirement.

6.The actual low period generated by the ATmega8535 Two-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be greater than 6 MHz for the low time requirement to be strictly met at fSCL = 100 kHz.

7.The actual low period generated by the ATmega8535 Two-wire Serial Interface is (1/fSCL - 2/fCK), thus the low time requirement will not be strictly met for fSCL > 308 kHz when fCK = 8 MHz. Still, ATmega8535 devices connected to the bus may communicate at full speed (400 kHz) with other ATmega8535 devices, as well as any other device with a proper tLOW acceptance margin.

Figure 128. Two-wire Serial Bus Timing

tof

tHIGH

tr

SCL

tLOW

tLOW

tSU;STA

tHD;STA

tHD;DAT

t

SDA

SU;DAT

tSU;STO

tBUF

256 ATmega8535(L)

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ATmega8535(L)

SPI Timing

Characteristics

See Figure 129 and Figure 130 for details.

Table 114. SPI Timing Parameters

		Description				Mode	Min	Typ	Max
1		SCK period				Master		See Table 59
2		SCK high/low				Master		50% duty cycle
3		Rise/Fall time				Master		TBD
4		Setup				Master		10
5		Hold				Master		10
6		Out to SCK				Master		5 • tSCK
7		SCK to out				Master		10
8		SCK to out high				Master		10
9		SS low to out				Slave		15		ns
10	SCK period					Slave	4 • tck
11	SCK high/low					Slave	2 • tck
12		Rise/Fall time				Slave		TBD
13		Setup				Slave	10
14	Hold					Slave	10
15	SCK to out					Slave		15
16	SCK to				high	Slave	20
				SS
17			high to tri-state			Slave		10
		SS
18	SS low to SCK					Slave	2 • tck

Figure 129. SPI Interface Timing Requirements (Master Mode)

SS

6

1

	SCK
	(CPOL = 0)
			2	2
	SCK
	(CPOL = 1)
	4	5		3
	MISO	MSB	...	LSB
	(Data Input)
			7	8
	MOSI	MSB	...	LSB
	(Data Output)

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2502B–AVR–09/02

Figure 130. SPI Interface Timing Requirements (Slave Mode)

	18
	SS
	9			10	16
	SCK
	(CPOL = 0)
			11	11
	SCK
	(CPOL = 1)
	13	14			12
	MOSI	MSB	...	LSB
	(Data Input)
			15		17
	MISO	MSB	...	LSB	X
	(Data Output)

258 ATmega8535(L)

2502B–AVR–09/02