Serial Downloading

Serial Programming Pin

Mapping

ATmega8535(L)

Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input), and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. NOTE, in Table 107 on page 247, the pin mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal SPI interface.

Table 107. Pin Mapping Serial Programming

Symbol	Pins	I/O	Description
MOSI	PB5	I	Serial Data in
MISO	PB6	O	Serial Data out
SCK	PB7	I	Serial Clock

Figure 124. Serial Programming and Verify(1)

										2.7 - 5.5V
									VCC
										2.7 - 5.5V(2)
MOSI								PB5	AVCC
MISO								PB6
	SCK							PB7
								XTAL1

RESET

GND

Notes: 1. If the device is clocked by the Internal Oscillator, it is no need to connect a clock source to the XTAL1 pin.

2. VCC - 0.3 < AVCC < VCC + 0.3. However, AVCC should always be within 2.7 - 5.5V.

When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip Erase operation turns the content of every memory location in both the Program and EEPROM arrays into 0xFF.

Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK) input are defined as follows:

Low:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck ≥ 12 MHz

High:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck ≥ 12 MHz

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Serial Programming

Algorithm

Data Polling Flash

When writing serial data to the ATmega8535, data is clocked on the rising edge of SCK.

When reading data from the ATmega8535, data is clocked on the falling edge of SCK. See Figure 125, Figure 126 and Table 110 for timing details.

To program and verify the ATmega8535 in the Serial Programming mode, the following sequence is recommended (See four byte instruction formats in Table 109):

1.Power-up sequence:

Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems, the programmer can not guarantee that SCK is held low during Power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to “0”.

2.Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI.

3.The serial programming instructions will not work if the communication is out of synchronization. When in synchronization the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command.

4.The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 6 LSB of the address and data together with the Load Program Memory Page instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 8 MSB of the address. If polling is not used,

the user must wait at least tWD_FLASH before issuing the next page. (See Table 108.) Accessing the serial programming interface before the Flash write operation completes can result in incorrect programming.

5.The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling is not

used, the user must wait at least tWD_EEPROM before issuing the next byte. (See Table 108). In a chip erased device, no 0xFFs in the data file(s) need to be programmed.

6.Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO.

7.At the end of the programming session, RESET can be set high to commence normal operation.

8.Power-off sequence (if needed): Set RESET to “1”.

Turn VCC power off.

When a page is being programmed into the Flash, reading an address location within the page being programmed will give the value 0xFF. At the time the device is ready for a new page, the programmed value will read correctly. This is used to determine when the next page can be written. Note that the entire page is written simultaneously and any address within the page can be used for polling. Data polling of the Flash will not work for the value 0xFF, so when programming this value, the user will have to wait for at

least tWD_FLASH before programming the next page. As a chip erased device contains 0xFF in all locations, programming of addresses that are meant to contain 0xFF, can be

skipped. See Table 108 for tWD_FLASH value.

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				ATmega8535(L)
	Data Polling EEPROM
		When a new byte has been written and is being programmed into EEPROM, reading the
		address location being programmed will give the value 0xFF. At the time the device is
		ready for a new byte, the programmed value will read correctly. This is used to deter-
		mine when the next byte can be written. This will not work for the value 0xFF, but the
		user should have the following in mind: As a chip erased device contains 0xFF in all
		locations, programming of addresses that are meant to contain 0xFF, can be skipped.
		This does not apply if the EEPROM is reprogrammed without chip erasing the device. In
		this case, data polling cannot be used for the value 0xFF, and the user will have to wait
		at least tWD_EEPROM before programming the next byte. See Table 108 for tWD_EEPROM
		value.
		Table 108. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location
		Symbol	Minimum Wait Delay
		tWD_FLASH		4.5 ms
		tWD_EEPROM		9.0 ms
		tWD_ERASE		9.0 ms

Figure 125. Serial Programming Waveforms

SERIAL DATA INPUT	MSB	LSB
(MOSI)
SERIAL DATA OUTPUT	MSB	LSB
(MISO)
SERIAL CLOCK INPUT
(SCK)
SAMPLE

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Table 109. Serial Programming Instruction Set

a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care

		Instruction Format
Instruction	Byte 1	Byte 2	Byte 3	Byte4		Operation
Programming Enable	1010 1100	0101 0011	xxxx xxxx	xxxx xxxx	Enable Serial Programming after
						RESET goes low.
Chip Erase	1010 1100	100x xxxx	xxxx xxxx	xxxx xxxx	Chip Erase EEPROM and Flash.
	0010 H000	0000 aaaa	bbbb bbbb	oooo oooo		Read H (high or low) data o from
Read Program Memory						Program memory at word address
						a:b.
	0100 H000	0000 xxxx	xxxb bbbb	iiii iiii		Write H (high or low) data i to
Load Program Memory						Program Memory page at word
						address b. Data low byte must be
Page
						loaded before Data high byte is
						applied within the same address.
Write Program Memory	0100 1100	0000 aaaa	bbbx xxxx	xxxx xxxx	Write Program Memory Page at
Page						address a:b.
Read EEPROM Memory	1010 0000	00xx xxxa	bbbb bbbb	oooo oooo		Read data o from EEPROM
						memory at address a:b.
Write EEPROM Memory	1100 0000	00xx xxxa	bbbb bbbb	iiii iiii		Write data i to EEPROM memory at
						address a:b.
	0101 1000	0000 0000	xxxx xxxx	xxoo oooo		Read Lock bits. “0” = programmed,
Read Lock Bits						“1” = unprogrammed. See Table
						96 on page 233 for details.
	1010 1100	111x xxxx	xxxx xxxx	11ii iiii		Write Lock bits. Set bits = “0” to
Write Lock Bits						program Lock bits. See Table 96
						on page 233 for details.
Read Signature Byte	0011 0000	00xx xxxx	xxxx xxbb	oooo oooo		Read Signature Byte o at address
						b.
	1010 1100	1010 0000	xxxx xxxx	iiii iiii		Set bits = “0” to program, “1” to
Write Fuse Bits						unprogram. See Table 99 on
						page 235 for details.
	1010 1100	1010 1000	xxxx xxxx	iiii iiii		Set bits = “0” to program, “1” to
Write Fuse High Bits						unprogram. See Table 98 on
						page 234 for details.
	0101 0000	0000 0000	xxxx xxxx	oooo oooo		Read Fuse bits. “0” = programmed,
Read Fuse Bits						“1” = unprogrammed. See Table
						99 on page 235 for details.
	0101 1000	0000 1000	xxxx xxxx	oooo oooo		Read Fuse high bits. “0” = pro-
Read Fuse High Bits						grammed, “1” = unprogrammed.
						See Table 98 on page 234 for
						details.
Read Calibration Byte	0011 1000	00xx xxxx	0000 00bb	oooo oooo		Read Calibration Byte

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ATmega8535(L)

Serial Programming	Figure 126. Serial Programming Timing
Characteristics

MOSI

tOVSH				tSHOX	tSLSH

SCK

tSHSL

MISO

tSLIV

Table 110. Serial Programming Characteristics, TA = -40°C to 85°C, VCC = 2.7 - 5.5V (Unless otherwise noted)(1)

Symbol	Parameter	Min	Typ	Max	Units
1/tCLCL	Oscillator Frequency (ATmega8535L)	0		8	MHz
tCLCL	Oscillator Period (ATmega8535L)	125			ns
	Oscillator Frequency (ATmega8535, VCC = 4.5 -
1/tCLCL	5.5V)	0		16	MHz
tCLCL	Oscillator Period (ATmega8535, VCC = 4.5 -
	5.5V)	67			ns
tSHSL	SCK Pulse Width High	2 tCLCL*			ns
tSLSH	SCK Pulse Width Low	2 tCLCL*			ns
tOVSH	MOSI Setup to SCK High	tCLCL			ns
tSHOX	MOSI Hold after SCK High	2 tCLCL			ns
tSLIV	SCK Low to MISO Valid		20		ns
Note: 1.	2 tCLCL for fck < 12 MHz, 3 tCLCL for fck >= 12 MHz

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