- •Features
- •Pin Configurations
- •Disclaimer
- •Overview
- •Block Diagram
- •AT90S8535 Compatibility
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •RESET
- •XTAL1
- •XTAL2
- •AVCC
- •AREF
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •I/O Memory
- •Clock Systems and their Distribution
- •CPU Clock – clkCPU
- •I/O Clock – clkI/O
- •Flash Clock – clkFLASH
- •ADC Clock – clkADC
- •Clock Sources
- •Default Clock Source
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Timer/Counter Oscillator
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Standby Mode
- •Extended Standby Mode
- •Analog-to-Digital Converter
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watchdog Timer
- •Safety Level 0
- •Safety Level 1
- •Safety Level 2
- •Interrupts
- •I/O-Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Unconnected pins
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions Of Port B
- •Alternate Functions of Port C
- •Alternate Functions of Port D
- •Port A Data Register – PORTA
- •Port B Data Register – PORTB
- •Port C Data Register – PORTC
- •Port D Data Register – PORTD
- •External Interrupts
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •16-bit Timer/Counter1
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Trigger Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •8-bit Timer/Counter2 with PWM and Asynchronous Operation
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Timer/Counter Prescaler
- •Slave Mode
- •Master Mode
- •SPI Control Register – SPCR
- •SPI Status Register – SPSR
- •SPI Data Register – SPDR
- •Data Modes
- •USART
- •Overview
- •AVR USART vs. AVR UART – Compatibility
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Sending Frames with 5 to 8 Data Bits
- •Sending Frames with 9 Data Bits
- •Parity Generator
- •Disabling the Transmitter
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Write Access
- •Read Access
- •Two-wire Serial Interface
- •Features
- •TWI Terminology
- •Electrical Interconnection
- •Transferring Bits
- •START and STOP Conditions
- •Address Packet Format
- •Data Packet Format
- •Overview of the TWI Module
- •SCL and SDA Pins
- •Bit Rate Generator Unit
- •Bus Interface Unit
- •Address Match Unit
- •Control Unit
- •TWI Register Description
- •TWI Bit Rate Register – TWBR
- •TWI Control Register – TWCR
- •TWI Status Register – TWSR
- •TWI Data Register – TWDR
- •Using the TWI
- •Transmission Modes
- •Master Transmitter Mode
- •Master Receiver Mode
- •Slave Receiver Mode
- •Slave Transmitter Mode
- •Miscellaneous States
- •Analog Comparator
- •Analog Comparator Multiplexed Input
- •Features
- •Operation
- •Starting a Conversion
- •Differential Gain Channels
- •Changing Channel or Reference Selection
- •ADC Input Channels
- •ADC Voltage Reference
- •ADC Noise Canceler
- •Analog Input Circuitry
- •ADC Accuracy Definitions
- •ADC Conversion Result
- •ADLAR = 0
- •ADLAR = 1
- •Boot Loader Features
- •Application Section
- •BLS – Boot Loader Section
- •Boot Loader Lock Bits
- •Performing a Page Write
- •Using the SPM Interrupt
- •Setting the Boot Loader Lock Bits by SPM
- •Reading the Fuse and Lock Bits from Software
- •Preventing Flash Corruption
- •Simple Assembly Code Example for a Boot Loader
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •Electrical Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •Two-wire Serial Interface Characteristics
- •ADC Characteristics – Preliminary Data
- •Instruction Set Summary
- •Ordering Information(1)
- •Packaging Information
- •Data Sheet Change Log for ATmega8535
- •Changes from Rev. 2502A-06/02 to Rev. 2502B-09/02
- •Table of Contents
ATmega8535(L)
Table 99. Fuse Low Byte
Fuse Low Byte |
Bit no |
Description |
Default Value |
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BODLEVEL |
7 |
Brown out detector trigger |
1 |
(unprogrammed) |
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level |
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BODEN |
6 |
Brown out detector enable |
1 |
(unprogrammed, BOD |
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disabled) |
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SUT1 |
5 |
Select start-up time |
1 |
(unprogrammed)(1) |
SUT0 |
4 |
Select start-up time |
0 |
(programmed)(1) |
CKSEL3 |
3 |
Select Clock source |
0 |
(programmed)(2) |
CKSEL2 |
2 |
Select Clock source |
0 |
(programmed)(2) |
CKSEL1 |
1 |
Select Clock source |
0 |
(programmed)(2) |
CKSEL0 |
0 |
Select Clock source |
1 |
(unprogrammed)(2) |
Notes: 1. The default value of SUT1..0 results in maximum start-up time. See Table 10 on page 28 for details.
2.The default setting of CKSEL3..0 results in internal RC Oscillator @ 1 MHz. See Table 2 on page 23 for details.
The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if Lock bit 1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits.
Latching of Fuses |
The Fuse values are latched when the device enters Programming mode and changes |
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of the Fuse values will have no effect until the part leaves Programming mode. This |
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does not apply to the EESAVE fuse which will take effect once it is programmed. The |
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fuses are also latched on Power-up in Normal mode. |
Signature Bytes
Calibration Byte
All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both Serial and Parallel mode, also when the device is locked. The three bytes reside in a separate address space.
For the ATmega8535 the signature bytes are:
1.0x000: 0x1E (indicates manufactured by Atmel)
2.0x001: 0x93 (indicates 8 KB Flash memory)
3.0x002: 0x08 (indicates ATmega8535 device when 0x001 is 0x93)
The ATmega8535 stores four different calibration values for the internal RC Oscillator. These bytes resides in the signature row high byte of the addresses 0x000, 0x0001, 0x0002, and 0x0003 for 1, 2, 4, and 8 MHz respectively. During Reset, the 1 MHz value is automatically loaded into the OSCCAL Register. If other frequencies are used, the calibration value has to be loaded manually, see “Oscillator Calibration Register – OSCCAL” on page 28 for details.
235
2502B–AVR–09/02
Parallel Programming
Parameters, Pin
Mapping, and
Commands
Signal Names
This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits in the ATmega8535. Pulses are assumed to be at least 250 ns unless otherwise noted.
In this section, some pins of the ATmega8535 are referenced by signal names describing their functionality during parallel programming, see Figure 115 and Table 100. Pins not described in the following table are referenced by pin names.
The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit coding is shown in Table 102.
When pulsing WR or OE, the command loaded determines the action executed. The different Commands are shown in Table 103.
Figure 115. Parallel Programming
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RDY/BSY |
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PD1 |
VCC |
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OE |
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PD2 |
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WR |
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PD3 |
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DATA |
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BS1 |
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PD4 |
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XA0 PD5
XA1 PD6
PAGEL PD7
+12 V RESET
BS2 PA0
XTAL1
GND
Table 100. Pin Name Mapping
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Signal Name in |
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Programming Mode |
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I/O |
Function |
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0: Device is busy programming, 1: Device is ready |
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RDY/BSY |
PD1 |
O |
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PD2 |
I |
Output Enable (Active low) |
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OE |
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PD3 |
I |
Write Pulse (Active low) |
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WR |
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BS1 |
PD4 |
I |
Byte Select 1 (“0” selects low byte, “1” selects high |
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XA0 |
PD5 |
I |
XTAL Action Bit 0 |
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XA1 |
PD6 |
I |
XTAL Action Bit 1 |
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PAGEL |
PD7 |
I |
Program Memory and EEPROM data Page Load |
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BS2 |
PA0 |
I |
Byte Select 2 (“0” selects low byte, “1” selects 2’nd |
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DATA |
PB7 - 0 |
I/O |
Bi-directional Data bus (Output when |
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236 ATmega8535(L)
2502B–AVR–09/02
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ATmega8535(L) |
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Table 101. Pin Values Used to Enter Programming Mode |
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PAGEL |
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Prog_enable[3] |
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XA1 |
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Prog_enable[2] |
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XA0 |
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Prog_enable[1] |
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BS1 |
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Prog_enable[0] |
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Table 102. XA1 and XA0 Coding |
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XA1 |
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XA0 |
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Action when XTAL1 is Pulsed |
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Load Flash or EEPROM Address (High or low address byte determined by |
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1 |
Load Data (High or Low data byte for Flash determined by BS1) |
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1 |
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Load Command |
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1 |
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No Action, Idle |
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Table 103. Command Byte Bit Coding |
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Command Byte |
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Command Executed |
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1000 0000 |
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Chip Erase |
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0100 0000 |
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Write Fuse Bits |
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0010 0000 |
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Write Lock Bits |
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0001 0000 |
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Write Flash |
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0001 0001 |
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Write EEPROM |
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0000 1000 |
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Read Signature Bytes and Calibration byte |
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0000 0100 |
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0000 0010 |
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Read Flash |
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0000 0011 |
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Read EEPROM |
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Table 104. |
No. of Words in a Page and no. of Pages in the Flash |
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Flash Size |
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Page Size |
PCWORD |
No. of Pages |
PCPAGE |
PCMSB |
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4K words (8K bytes) |
32 words |
PC[4:0] |
128 |
PC[11:5] |
11 |
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Table 105. |
No. of Words in a Page and no. of Pages in the EEPROM |
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EEPROM Size |
Page Size |
PCWORD |
No. of Pages |
PCPAGE |
EEAMSB |
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512 bytes |
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4 bytes |
EEA[1:0] |
128 |
EEA[8:2] |
8 |
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237
2502B–AVR–09/02