- •Features
- •Pin Configurations
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port A (PA2..PA0)
- •Port B (PB7..PB0)
- •Port D (PD6..PD0)
- •RESET
- •XTAL1
- •XTAL2
- •Disclaimer
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •Atomic Byte Programming
- •Split Byte Programming
- •Erase
- •Write
- •I/O Memory
- •General Purpose I/O Registers
- •Clock Systems and their Distribution
- •Clock Sources
- •Default Clock Source
- •Crystal Oscillator
- •External Clock
- •Idle Mode
- •Power-down Mode
- •Standby Mode
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Interrupts
- •I/O-Ports
- •Introduction
- •Configuring the Pin
- •Toggling the Pin
- •Reading the Pin Value
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions of Port B
- •Alternate Functions of Port D
- •Register Description for I/O-Ports
- •External Interrupts
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •16-bit Timer/Counter1
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Trigger Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •USART
- •Overview
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Sending Frames with 5 to 8 Data Bit
- •Sending Frames with 9 Data Bit
- •Parity Generator
- •Disabling the Transmitter
- •Receiving Frames with 5 to 8 Data Bits
- •Receiving Frames with 9 Data Bits
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Overview
- •Functional Descriptions
- •Three-wire Mode
- •SPI Slave Operation Example
- •Two-wire Mode
- •Start Condition Detector
- •Alternative USI Usage
- •4-bit Counter
- •12-bit Timer/Counter
- •Software Interrupt
- •Analog Comparator
- •debugWIRE On-chip Debug System
- •Features
- •Overview
- •Physical Interface
- •Software Break Points
- •Limitations of debugWIRE
- •debugWIRE Related Register in I/O Memory
- •Performing a Page Write
- •Reading the Fuse and Lock Bits from Software
- •Preventing Flash Corruption
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Page Size
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •Active Supply Current
- •Idle Supply Current
- •Power-down Supply Current
- •Standby Supply Current
- •Pin Pull-up
- •Pin Driver Strength
- •Internal Oscillator Speed
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Errata
- •ATtiny2313 Rev B
- •ATtiny2313 Rev A
- •Changes from Rev. 2514F-08/04 to Rev. 2514G-10/04
- •Changes from Rev. 2514F-08/04 to Rev. 2514G-10/04
- •Changes from Rev. 2514E-04/04 to Rev. 2514F-08/04
- •Changes from Rev. 2514D-03/04 to Rev. 2514E-04/04
- •Changes from Rev. 2514C-12/03 to Rev. 2514D-03/04
- •Changes from Rev. 2514B-09/03 to Rev. 2514C-12/03
- •Changes from Rev. 2514A-09/03 to Rev. 2514B-09/03
- •Table of Contents
Features
•Utilizes the AVR® RISC Architecture
•AVR – High-performance and Low-power RISC Architecture
–120 Powerful Instructions – Most Single Clock Cycle Execution
–32 x 8 General Purpose Working Registers
–Fully Static Operation
–Up to 20 MIPS Throughput at 20 MHz
•Data and Non-volatile Program and Data Memories
–2K Bytes of In-System Self Programmable Flash
Endurance 10,000 Write/Erase Cycles
–128 Bytes In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles
–128 Bytes Internal SRAM
–Programming Lock for Flash Program and EEPROM Data Security
•Peripheral Features
–One 8-bit Timer/Counter with Separate Prescaler and Compare Mode
–One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Modes
–Four PWM Channels
–On-chip Analog Comparator
–Programmable Watchdog Timer with On-chip Oscillator
–USI – Universal Serial Interface
–Full Duplex USART
•Special Microcontroller Features
–debugWIRE On-chip Debugging
–In-System Programmable via SPI Port
–External and Internal Interrupt Sources
–Low-power Idle, Power-down, and Standby Modes
–Enhanced Power-on Reset Circuit
–Programmable Brown-out Detection Circuit
–Internal Calibrated Oscillator
•I/O and Packages
–18 Programmable I/O Lines
–20-pin PDIP, 20-pin SOIC, 20-pad QFN/MLF
•Operating Voltages
–1.8 - 5.5V (ATtiny2313V)
–2.7 - 5.5V (ATtiny2313)
•Speed Grades
–ATtiny2313V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V
–ATtiny2313: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
•Typical Power Consumption
–Active Mode
1 MHz, 1.8V: 230 µA
32 kHz, 1.8V: 20 µA (including oscillator)
–Power-down Mode
<0.1 µA at 1.8V
8-bit
Microcontroller with 2K Bytes In-System Programmable Flash
ATtiny2313/V
Preliminary
Rev. 2543H–AVR–02/05