AMBA AHB

3.12.4Bus handover with split transfers

The protocol requires that a master performs an IDLE transfer immediately after receiving a SPLIT or RETRY response allowing the bus to be transferred to another master. Figure 3-20 shows the sequence of events that occur for a split transfer.

T1

HCLK

HGRANT

HTRAN[1:0]

HADDR[31:0]

HBURST[2:0]

HWRITE

HSIZE[2:0]

HPROT[3:0]

HREADY

HRESP[1:0]

	Slave
	signals
T2	split	T3
NONSEQ	SEQ
A	A + 4
Control (A)
	SPLIT

Arbiter
changes
grant	T4
IDLE
SPLIT

New master
drives
address	T5
NONSEQ
B
Control (B)
OKAY

Figure 3-20 Handover after split transfer

The following points should be noted:

•The address for the transfer is on the bus after time T1. The slave returns the two-cycle SPLIT response after the clock edges at T2 and T3.

•At the end of the first response cycle, T3, the master can detect that the transfer will be SPLIT and so it changes the control signals for the following transfer to show an IDLE transfer.

•Also at time T3 the arbiter samples the response signals and determines that the transfer has been SPLIT. The arbiter can then adjust the arbitration priorities and the grant signals change during the following cycle, such that the new master can be granted the address bus after time T4.

•The new master is guaranteed immediate access because the IDLE transfer always completes in a single cycle.

ARM IHI 0011A

© Copyright ARM Limited 1999. All rights reserved.

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