AMBA ASB

4.2AMBA ASB description

The ASB is a high-performance pipelined bus, which supports multiple bus masters.

The basic flow of the bus operation is:

1.The arbiter determines which master is granted access to the bus.

2.When granted, a master initiates transfers on the bus.

3.The decoder uses the high order address lines to select a bus slave.

4.The slave provides a transfer response back to the bus master and data is transferred between the master and slave.

There are three types of transfer that can occur on the ASB:

NONSEQUENTIAL

Used for single transfers or for the first transfer of a burst.

SEQUENTIAL

Used for transfers in a burst. The address of a SEQUENTIAL transfer is always related to the previous transfer.

ADDRESS-ONLY

Used when no data movement is required. The three main uses for ADDRESS-ONLY transfers are for IDLE cycles, for bus master HANDOVER cycles, and for speculative address decoding without committing to a data transfer.

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© Copyright ARM Limited 1999. All rights reserved.

ARM IHI 0011A

AMBA ASB

Figure 4-2 shows the use of NONSEQUENTIAL and SEQUENTIAL transfers to perform a burst transaction.

		Transfer 1		Transfer 2	Transfer 3		Transfer 4
BCLK
BTRAN[1:0]	N-TRAN	S-TRAN	S-TRAN	S-TRAN		S-TRAN	S-TRAN
BA[31:0]		Addr	Addr + 4		Addr + 8	Addr + C
BWRITE
BSIZE[1:0]				Control
BPROT[1:0]
DSELx
BWAIT
BERROR		WAIT	DONE	DONE	DONE		DONE
BLAST
BD[31:0]			Data		Data	Data	Data
			(A)		(A+4)	(A+8)	(A+C)

Figure 4-2 ASB transfers

The burst starts with a NONSEQUENTIAL transfer to address A. The following

SEQUENTIAL transfers are to successive addresses A+4, A+8 and A+12.

ARM IHI 0011A

© Copyright ARM Limited 1999. All rights reserved.

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