AMBA Test Methodology

6.8Example AMBA ASB test sequences

Example ASB test sequences are described under the following headings:

•Entering test mode

•Address vectors on page 6-28

•Control vectors on page 6-29

•Write test vectors on page 6-31

•Changing burst direction on page 6-36

•Exiting test mode on page 6-37.

6.8.1Entering test mode

Test mode is entered, as shown in Figure 6-10, using the following sequence:

1.TREQA is asserted to request test bus access.

2.Test mode is entered when the TIC has been granted the internal bus and this is indicated by the assertion of the TACK signal.

3.At this point TCLK will become the source of the internal BCLK signal.

4.When test mode has been entered TREQB is asserted to initiate an address vector.

Test bus

requested

TCLK

TREQA

TREQB

TACK

TBUS

Test bus	Address
available	vector
	Address

Figure 6-10 Test start sequence

ARM IHI 0011A

© Copyright ARM Limited 1999. All rights reserved.

6-27

AMBA Test Methodology

6.8.2Address vectors

An address vector must be applied before a read or write operation can occur. Figure 6-11 shows an example of a single address vector followed by a write vector, the following sequence occurs:

1.TREQA and TREQB are both asserted HIGH to indicate an address vector next cycle.

2.In the next cycle the address is applied, while TREQA and TREQB change to indicate the type of test vector that will follow. During this cycle the address appears on the address bus.

3.In the next cycle the write (or read) vector is applied.

	C0	C1	C2
TCLK
TREQA
TREQB
TACK
TBUS		Address	Write 1
		vector	vector
BTRAN[1:0]	A-TRAN	N-TRAN
BA			A
BD			Write
			data

Figure 6-11 Address vector

6-28

© Copyright ARM Limited 1999. All rights reserved.

ARM IHI 0011A

AMBA Test Methodology

6.8.3Control vectors

A control vector must always follow an address vector. Figure 6-12 shows an address and control vector sequence followed by a write vector. The following sequence occurs:

1.TREQA and TREQB both remain HIGH after the address vector has ended to indicate a control vector next cycle.

2.In the next cycle control information is applied to TBUS[31:0], while TREQA and TREQB change to reflect the type of test vector that will follow. During this cycle any internal signals, which have been affected by the control vector, will change.

	C0	C1	C2
TCLK
TREQA
TREQB
TACK
TBUS		Address	Control	Write
		vector	vector	vector
BTRAN[1:0]	A-TRAN	A-TRAN	N-TRAN
BA			A
BSIZE
BD				Write
				data

Figure 6-12 Control vector

ARM IHI 0011A

© Copyright ARM Limited 1999. All rights reserved.

6-29

AMBA Test Methodology

Figure 6-13 shows an example of a transfer following an invalid control vector. The TIC performs a SEQUENTIAL transfer on the internal bus because the control signals have not changed.

	C0	C1	C2
TCLK
TREQA
TREQB
TACK
TBUS		Address	Control	Write
		vector	vector	vector
BTRAN[1:0]	A-TRAN	A-TRAN	S-TRAN
BA			A
BSIZE
BD				Write
				data

Figure 6-13 Invalid control vector

6-30

© Copyright ARM Limited 1999. All rights reserved.

ARM IHI 0011A