AMBA ASB

4.7Reset operation

The reset signal, BnRES, is active LOW and may be asserted asynchronously to guarantee the bus is in a safe state. During reset the following actions occur on the bus:

•the arbiter grants the default bus master

•the default bus master must:

•drive BTRAN to indicate ADDRESS-ONLY transfer

•drive BLOK LOW to allow arbitration.

•all other bus masters tristate shared bus signals

•the decoder must:

•de-assert all slave select signals, DSELx

•provide the appropriate transfer response.

•all slaves tristate shared bus signals.

4.7.1Exit from reset

Figure 4-11 shows an example of the exit from reset sequence.

	C0
BCLK
BnRES
BTRAN[1:0]	A-TRAN
BA[31:0]
BWAIT
BERROR	DONE
BLAST

C1	C2	C3
	S-TRAN
	Address
DONE	WAIT	DONE

Figure 4-11 Exiting from reset

The following points should be noted:

• During cycle C1 BnRES is de-asserted during the clock LOW phase.

ARM IHI 0011A

© Copyright ARM Limited 1999. All rights reserved.

4-23

AMBA ASB

•During the clock HIGH phase of cycle C1 the default bus master may drive the BTRAN signal to indicate that it wishes to start a transfer.

•The transfer will start during cycle C2 and, in the example shown, the transfer is waited and continues into cycle C3.

4-24

© Copyright ARM Limited 1999. All rights reserved.

ARM IHI 0011A