AMBA AHB

3.18 AHB bus slave

An AHB bus slave responds to transfers initiated by bus masters within the system. The slave uses a HSELx select signal from the decoder to determine when it should respond to a bus transfer. All other signals required for the transfer, such as the address and control information, will be generated by the bus master.

3.18.1Interface diagram

Figure 3-23 shows an AHB bus slave interface.

Select	HSELx
	HADDR[31:0]
Address	HWRITE
and	HTRANS[1:0]				HREADY
control						Transfer
				AHB	HRESP[1:0]
	HSIZE[2:0]					response
				slave
	HBURST[2:0]
Data	HWDATA[31:0]				HRDATA[31:0]	Data
Reset	HRESETn
Clock	HCLK
	HMASTER[3:0]
				Split-capable
					HSPLITx[15:0]
				slave
	HMASTLOCK

Figure 3-23 AHB bus slave interface

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AMBA AHB

3.18.2Timing diagrams

The following diagrams show the timing parameters related to an access to an AHB bus slave operating in an AMBA system:

•Figure 3-24 shows the AHB slave reset timing parameters

•Figure 3-25 shows the main AHB slave timing parameters

•Figure 3-26 shows the additional timing parameters for split-capable AHB slaves.

HCLK
HRESETn
		Tisrst
	Tihrst
	Figure 3-24 AHB slave reset timing
HCLK
HSELx
		Tihsel
	Tissel
HTRANS[1:0]	NONSEQ
		Tihtr
	Tistr
HADDR[31:0]	A
		Tiha
	Tisa
HWRITE
HSIZE[2:0]	Control
HBURST[2:0]		Tihctl
	Tisctl
HWDATA[31:0]		Data
		(A)
		Tihwd
	Tiswd
HREADY
	Tovrdy	Tohrdy
HRESP[1:0]		OKAY
	Tovrsp	Tohrsp
HRDATA[31:0]		Data
		(A)
		Tohrd
	Tovrd

Figure 3-25 AHB timing parameters

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ARM IHI 0011A

AMBA AHB

HCLK

HMASTER[3:0]

Tihmst

Tismst

HMASTLOCK

Tihmlck

Tismlck

HSPLITx[15:0]
Tovsplt	Tohsplt

Figure 3-26 Additional split-capable slave parameters

3.18.3Timing parameters

The timing parameters related to an AHB bus slave are given for input signals in

Table 3-8 and for output signals in Table 3-9.

	Table 3-8 AHB slave input parameters
Parameter	Description
Tclk	HCLK minimum clock period
Tisrst	HRESETn deasserted setup time before HCLK
Tihrst	HRESETn deasserted hold time after HCLK
Tissel	HSELx setup time before HCLK
Tihsel	HSELx hold time after HCLK
Tistr	Transfer type setup time before HCLK
Tihtr	Transfer type hold time after HCLK
Tisa	HADDR[31:0] setup time before HCLK
Tiha	HADDR[31:0] hold time after HCLK
Tisctl	HWRITE, HSIZE[2:0] and HBURST[2:0] control signal setup time
	before HCLK

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AMBA AHB

	Table 3-8 AHB slave input parameters (continued)
Parameter	Description
Tihctl	HWRITE, HSIZE[2:0] and HBURST[2:0] control signal hold time
	after HCLK
Tiswd	Write data setup time before HCLK
Tihwd	Write data hold time after HCLK
Tisrdy	Ready setup time before HCLK
Tihrdy	Ready hold time after HCLK
Tismst	Master number setup time before HCLK (SPLIT-capable only)
Tihmst	Master number hold time after HCLK (SPLIT-capable only)
Tismlck	Master locked setup time before HCLK (SPLIT-capable only)
Tihmlck	Master locked hold time after HCLK (SPLIT-capable only)
	Table 3-9 AHB slave output parameters
Parameter	Description
Tovrsp	Response valid time after HCLK
Tohrsp	Response hold time after HCLK
Tovrdy	Ready valid time after HCLK
Tohrdy	Ready hold time after HCLK
Tovsplt	Split valid time after HCLK (SPLIT-capable only)
Tohsplt	Split hold time after HCLK (SPLIT-capable only)

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ARM IHI 0011A