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4.8.9Address and control signal timing

The address and control information is generated by the bus master from the rising edge of BCLK. However, the timing of the address and control information is considered separately for NONSEQUENTIAL and SEQUENTIAL transfer types. This is because a bus master will typically have significantly different timing parameters in each case.

It is a common characteristic that bus masters will have fast address and control output valid timings for SEQUENTIAL transfers, as shown in Figure 4-14. This is because a bus master is usually able to generate a SEQUENTIAL address well before the start of the transfer and therefore the output valid time from the bus master is mainly dependent on the time required to drive the new value onto the bus.

	BCLK
	BTRAN[1:0]	S-TRAN
	BA[31:0]	Sequential
		address
	BWRITE	Sequential
	BSIZE[1:0]
		control
	BPROT[1:0]

Start of transfer

Figure 4-14 Sequential address and control timing

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For NONSEQUENTIAL transfers the bus master will often have significantly slower output valid times for address and control signals, compared to those for SEQUENTIAL transfers and this is shown in Figure 4-15.

	BCLK
	BTRAN [1:0]	N-TRAN
	BA[31:0]	Nonsequential
		address

BWRITE

Nonsequential

BSIZE[1:0] control

BPROT[1:0]

Start of transfer

	BCLK
	BTRAN [1:0]	N-TRAN
	BA [31:0]	Nonsequential
		address

BWRITE

Nonsequential

BSIZE [1:0] control

BPROT [1:0]

Start of transfer

Figure 4-15 Nonsequential address and control timing with low-frequency and high-frequency clocks

In systems where the clock frequency is approaching the maximum possible, it is common for the address and control output valid time to be greater than a clock phase, thus resulting in the address not becoming valid until the BCLK LOW phase at the start of the transfer, as shown in Figure 4-15.

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For ADDRESS-ONLY transfers the address and control information is not valid. In the special case of the ADDRESS-ONLY followed immediately by a SEQUENTIAL transfer, as shown in Figure 4-16, the bus master generates the address and control information during the ADDRESS-ONLY transfer, such that it is valid throughout the BCLK HIGH phase before the start of the SEQUENTIAL transfer.

BCLK

BTRAN[1:0]

A-TRAN

S-TRAN

BA[31:0]

Address

BWRITE

BSIZE[1:0] Control

BPROT[1:0]

Start of transfer

Figure 4-16 Address-only followed by sequential transfer address and control timing

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4.8.10Tristate enable of address and control signals

A bus master may only drive the address and control signals when the bus master is granted the bus. To allow for a period of bus turnaround, when a bus master is first granted the bus it will not drive in the BCLK HIGH phase before the first transfer.

Instead, the bus master must always start a period of bus ownership with an ADDRESSONLY transfer and the address and control signals are not driven until the BCLK LOW phase of the ADDRESS-ONLY transfer (see Figure 4-17).

Previous bus master

New bus master

BCLK
BTRAN[1:0]	A-TRAN	S-TRAN
BA[31:0]
BWRITE
BSIZE[1:0]
BPROT[1:0]
	Previous transfer	Address-only after	Sequential transfer
	completes	bus turnaround

Figure 4-17 Address and control signals during bus master handover

For multi-master systems:

•When the master is first granted, the signals are not driven until the first LOW phase of BCLK when the master becomes active on the bus.

•When a bus master is granted the bus it drives the address and control signals during both phases of BCLK.

•The bus master stops driving the signals in the last BCLK HIGH phase, when the master loses mastership of the bus.

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