ATmega8A

Table 25-2. External RC Oscillator, Typical Frequencies

R [kΩ](1)	C [pF]	f(2)
33	22	650 kHz
10	22	2.0 MHz

Notes: 1. R should be in the range 3 kΩ - 100 kΩ, and C should be at least 20 pF. The C values given in the table includes pin capacitance. This will vary with package type.

2.The frequency will vary with package type and board layout.

25.5System and Reset Characteristics

Table 25-3.		Reset, Brown-out and Internal Voltage Reference Characteristics
Symbol		Parameter				Condition	Min	Typ	Max	Units
		Power-on Reset Threshold Voltage						1.4	2.3	V
		(rising)(1)
VPOT
		Power-on Reset Threshold Voltage						1.3	2.3	V
		(falling)
VRST			Pin Threshold Voltage				0.2		0.9	VCC
		RESET
tRST		Minimum pulse width on			Pin				1.5	µs
				RESET
VBOT		Brown-out Reset Threshold Voltage(2)				BODLEVEL = 1	2.40	2.60	2.90	V
						BODLEVEL = 0	3.70	4.00	4.50
tBOD		Minimum low voltage period for Brown-				BODLEVEL = 1		2		µs
		out Detection
						BODLEVEL = 0		2		µs
VHYST		Brown-out Detector hysteresis						130		mV
VBG		Bandgap reference voltage					1.15	1.23	1.35	V
tBG		Bandgap reference start-up time						40	70	µs
IBG		Bandgap reference current consumption						10		µs

Notes: 1. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling).

2.VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to VCC = VBOT during the production test. This guarantees that a Brown-out Reset will occur before VCC drops to a voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 1 and BODLEVEL = 0 for ATmega8A.

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25.6Two-wire Serial Interface Characteristics

Table 25-4 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega8A Two-wire Serial Interface meets or exceeds these requirements under the noted conditions.

Timing symbols refer to Figure 25-3.

Table 25-4. Two-wire Serial Bus Requirements

Symbol

Parameter

Condition

Min

Max

Units

VIL

Input Low-voltage

-0.5

0.3 VCC

V

VIH

Input High-voltage

0.7 VCC

VCC + 0.5

V

(1)

Hysteresis of Schmitt Trigger Inputs

(2)

–

V

Vhys

0.05 VCC

V

(1)

Output Low-voltage

3 mA sink current

0

0.4

V

OL

tr(1)

Rise Time for both SDA and SCL

20 + 0.1Cb(3)(2)

300

ns

t

of

(1)

Output Fall Time from V

to V

10 pF < C < 400 pF(3)

20 + 0.1C

(3)(2)

250

ns

IHmin

ILmax

b

b

tSP(1)

Spikes Suppressed by Input Filter

0

50(2)

ns

Ii

Input Current each I/O Pin

0.1VCC < Vi < 0.9VCC

-10

10

µA

C

(1)

Capacitance for each I/O Pin

–

10

pF

i

f

SCL

SCL Clock Frequency

f

(4) > max(16f

SCL

, 250kHz)(5)

0

400

kHz

CK

fSCL ≤ 100 kHz

VCC – 0,4V

1000ns

Ω

----------------------------

-------------------

Rp

Value of Pull-up resistor

3mA

Cb

fSCL > 100 kHz

VCC – 0,4V

300ns

Ω

----------------------------

---------------

3mA

Cb

tHD;STA

Hold Time (repeated) START Condition

fSCL ≤ 100 kHz

4.0

–

µs

fSCL > 100 kHz

0.6

–

µs

tLOW

Low Period of the SCL Clock

fSCL ≤ 100 kHz(6)

4.7

–

µs

f

> 100 kHz(7)

1.3

–

µs

SCL

tHIGH

High period of the SCL clock

fSCL ≤ 100 kHz

4.0

–

µs

fSCL > 100 kHz

0.6

–

µs

tSU;STA

Set-up time for a repeated START condition

fSCL ≤ 100 kHz

4.7

–

µs

fSCL > 100 kHz

0.6

–

µs

tHD;DAT

Data hold time

fSCL ≤ 100 kHz

0

3.45

µs

fSCL > 100 kHz

0

0.9

µs

tSU;DAT

Data setup time

fSCL ≤ 100 kHz

250

–

ns

fSCL > 100 kHz

100

–

ns

tSU;STO

Setup time for STOP condition

fSCL ≤ 100 kHz

4.0

–

µs

fSCL > 100 kHz

0.6

–

µs

tBUF

Bus free time between a STOP and START

fSCL ≤ 100 kHz

4.7

–

µs

condition

fSCL > 100 kHz

1.3

–

µs

Notes: 1.

In ATmega8A, this parameter is characterized and not 100% tested.

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2.Required only for fSCL > 100 kHz.

3.Cb = capacitance of one bus line in pF.

4.fCK = CPU clock frequency

5.This requirement applies to all ATmega8A Two-wire Serial Interface operation. Other devices connected to the Two-wire Serial Bus need only obey the general fSCL requirement.

6.The actual low period generated by the ATmega8A Two-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be greater than 6 MHz for the low time requirement to be strictly met at fSCL = 100 kHz.

7.The actual low period generated by the ATmega8A Two-wire Serial Interface is (1/fSCL - 2/fCK), thus the low time requirement will not be strictly met for fSCL > 308 kHz when fCK = 8 MHz. Still, ATmega8A devices connected to the bus may communicate at full speed (400 kHz) with other ATmega8A devices, as well as any other device with a proper tLOW acceptance margin.

Figure 25-3. Two-wire Serial Bus Timing

tof

tHIGH

tr

SCL

tLOW

tLOW

tSU;STA

tHD;STA

tHD;DAT

t

SDA

SU;DAT

tSU;STO

tBUF

25.7SPI Timing Characteristics

See Figure 25-4 and Figure 25-5 for details.

Table 25-5.

SPI Timing Parameters

Description

Mode

Min

Typ

Max

1

SCK period

Master

See Table 18-4

2

SCK high/low

Master

50% duty cycle

3

Rise/Fall time

Master

3.6

4

Setup

Master

10

5

Hold

Master

10

6

Out to SCK

Master

0.5 • tSCK

7

SCK to out

Master

10

8

SCK to out high

Master

10

9

low to out

Slave

15

SS

ns

10

SCK period

Slave

4 • tck

11

SCK high/low(1)

Slave

2 • t

ck

12

Rise/Fall time

Slave

1.6

13

Setup

Slave

10

14

Hold

Slave

10

15

SCK to out

Slave

15

16

SCK to

high

Slave

20

SS

17

high to tri-state

Slave

10

SS

18

low to SCK

Salve

2 • tck

SS

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Note: 1. In SPI Programming mode the minimum SCK high/low period is:

-2tCLCL for fCK < 12 MHz

-3tCLCL for fCK > 12 MHz

Figure 25-4. SPI interface timing requirements (Master Mode)

SS

SCK (CPOL = 0)

SCK (CPOL = 1)

MISO

(Data Input)

MOSI

(Data Output)

6			1
		2	2
4	5		3
	MSB	...	LSB
		7	8
	MSB	...	LSB

Figure 25-5. SPI interface timing requirements (Slave Mode)

SS

SCK (CPOL = 0)

SCK (CPOL = 1)

MOSI

(Data Input)

MISO

(Data Output)

18
9			10	16
		11	11
13	14			12
	MSB	...	LSB
		15		17
	MSB	...	LSB	X

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