- •Features
- •1. Pin Configurations
- •2. Overview
- •2.1 Block Diagram
- •2.2 Pin Descriptions
- •2.2.3 Port B (PB7:PB0) – XTAL1/XTAL2/TOSC1/TOSC2
- •2.2.4 Port C (PC5:PC0)
- •2.2.5 PC6/RESET
- •2.2.6 Port D (PD7:PD0)
- •2.2.7 RESET
- •2.2.9 AREF
- •2.2.10 ADC7:6 (TQFP and QFN/MLF Package Only)
- •3. Resources
- •4. Data Retention
- •5. About Code Examples
- •6. AVR CPU Core
- •6.1 Overview
- •6.2 Arithmetic Logic Unit – ALU
- •6.3 Status Register
- •6.3.1 SREG – The AVR Status Register
- •6.4 General Purpose Register File
- •6.5 Stack Pointer
- •6.5.1 SPH and SPL – Stack Pointer High and Low Register
- •6.6 Instruction Execution Timing
- •6.7 Reset and Interrupt Handling
- •6.7.1 Interrupt Response Time
- •7. AVR Memories
- •7.1 Overview
- •7.3 SRAM Data Memory
- •7.3.1 Data Memory Access Times
- •7.4 EEPROM Data Memory
- •7.4.1 EEPROM Read/Write Access
- •7.5 I/O Memory
- •7.6 Register Description
- •7.6.1 EEARH and EEARL – The EEPROM Address Register
- •7.6.2 EEDR – The EEPROM Data Register
- •7.6.3 EECR – The EEPROM Control Register
- •7.6.5 Preventing EEPROM Corruption
- •8. System Clock and Clock Options
- •8.1 Clock Systems and their Distribution
- •8.2 Clock Sources
- •8.3 Crystal Oscillator
- •8.5 External RC Oscillator
- •8.6 Calibrated Internal RC Oscillator
- •8.7 External Clock
- •8.8 Timer/Counter Oscillator
- •8.9 Register Description
- •8.9.1 OSCCAL – Oscillator Calibration Register
- •9. Power Management and Sleep Modes
- •9.1 Sleep Modes
- •9.2 Idle Mode
- •9.3 ADC Noise Reduction Mode
- •9.6 Standby Mode
- •9.7 Minimizing Power Consumption
- •9.7.2 Analog Comparator
- •9.7.4 Internal Voltage Reference
- •9.7.5 Watchdog Timer
- •9.7.6 Port Pins
- •9.8 Register Description
- •9.8.1 MCUCR – MCU Control Register
- •10. System Control and Reset
- •10.1 Resetting the AVR
- •10.2 Reset Sources
- •10.2.2 External Reset
- •10.2.4 Watchdog Reset
- •10.3 Internal Voltage Reference
- •10.4 Watchdog Timer
- •10.5 Timed Sequences for Changing the Configuration of the Watchdog Timer
- •10.5.1 Safety Level 1 (WDTON Fuse Unprogrammed)
- •10.5.2 Safety Level 2 (WDTON Fuse Programmed)
- •10.6 Register Description
- •10.6.1 MCUCSR – MCU Control and Status Register
- •10.6.2 WDTCR – Watchdog Timer Control Register
- •11. Interrupts
- •11.1 Interrupt Vectors in ATmega8A
- •11.1.1 Moving Interrupts Between Application and Boot Space
- •11.2 Register Description
- •11.2.1 GICR – General Interrupt Control Register
- •12. I/O Ports
- •12.1 Overview
- •12.2 Ports as General Digital I/O
- •12.2.1 Configuring the Pin
- •12.2.2 Reading the Pin Value
- •12.2.3 Digital Input Enable and Sleep Modes
- •12.2.4 Unconnected pins
- •12.3 Alternate Port Functions
- •12.3.1 SFIOR – Special Function IO Register
- •12.3.2 Alternate Functions of Port B
- •12.3.3 Alternate Functions of Port C
- •12.3.4 Alternate Functions of Port D
- •12.4 Register Description
- •12.4.1 PORTB – The Port B Data Register
- •12.4.2 DDRB – The Port B Data Direction Register
- •12.4.3 PINB – The Port B Input Pins Address
- •12.4.4 PORTC – The Port C Data Register
- •12.4.5 DDRC – The Port C Data Direction Register
- •12.4.6 PINC – The Port C Input Pins Address
- •12.4.7 PORTD – The Port D Data Register
- •12.4.8 DDRD – The Port D Data Direction Register
- •12.4.9 PIND – The Port D Input Pins Address
- •13. External Interrupts
- •13.1 Register Description
- •13.1.1 MCUCR – MCU Control Register
- •13.1.2 GICR – General Interrupt Control Register
- •13.1.3 GIFR – General Interrupt Flag Register
- •14. 8-bit Timer/Counter0
- •14.1 Features
- •14.2 Overview
- •14.2.1 Registers
- •14.2.2 Definitions
- •14.3 Timer/Counter Clock Sources
- •14.4 Counter Unit
- •14.5 Operation
- •14.6 Timer/Counter Timing Diagrams
- •14.7 Register Description
- •14.7.1 TCCR0 – Timer/Counter Control Register
- •14.7.2 TCNT0 – Timer/Counter Register
- •14.7.3 TIMSK – Timer/Counter Interrupt Mask Register
- •14.7.4 TIFR – Timer/Counter Interrupt Flag Register
- •15. Timer/Counter0 and Timer/Counter1 Prescalers
- •15.1 Overview
- •15.2 Internal Clock Source
- •15.3 Prescaler Reset
- •15.4 External Clock Source
- •15.5 Register Description
- •15.5.1 SFIOR – Special Function IO Register
- •16. 16-bit Timer/Counter1
- •16.1 Features
- •16.2 Overview
- •16.2.1 Registers
- •16.2.2 Definitions
- •16.2.3 Compatibility
- •16.3.1 Reusing the Temporary High Byte Register
- •16.4 Timer/Counter Clock Sources
- •16.5 Counter Unit
- •16.6 Input Capture Unit
- •16.6.1 Input Capture Pin Source
- •16.6.2 Noise Canceler
- •16.6.3 Using the Input Capture Unit
- •16.7 Output Compare Units
- •16.7.1 Force Output Compare
- •16.7.2 Compare Match Blocking by TCNT1 Write
- •16.7.3 Using the Output Compare Unit
- •16.8 Compare Match Output Unit
- •16.8.1 Compare Output Mode and Waveform Generation
- •16.9 Modes of Operation
- •16.9.1 Normal Mode
- •16.9.2 Clear Timer on Compare Match (CTC) Mode
- •16.9.3 Fast PWM Mode
- •16.9.4 Phase Correct PWM Mode
- •16.9.5 Phase and Frequency Correct PWM Mode
- •16.10 Timer/Counter Timing Diagrams
- •16.11 Register Description
- •16.11.1 TCCR1A – Timer/Counter 1 Control Register A
- •16.11.2 TCCR1B – Timer/Counter 1 Control Register B
- •16.11.3 TCNT1H and TCNT1L – Timer/Counter 1
- •16.11.4 OCR1AH and OCR1AL– Output Compare Register 1 A
- •16.11.5 OCR1BH and OCR1BL – Output Compare Register 1 B
- •16.11.6 ICR1H and ICR1L – Input Capture Register 1
- •17. 8-bit Timer/Counter2 with PWM and Asynchronous Operation
- •17.1 Features
- •17.2 Overview
- •17.2.1 Registers
- •17.2.2 Definitions
- •17.3 Timer/Counter Clock Sources
- •17.4 Counter Unit
- •17.5 Output Compare Unit
- •17.5.1 Force Output Compare
- •17.5.2 Compare Match Blocking by TCNT2 Write
- •17.5.3 Using the Output Compare Unit
- •17.6 Compare Match Output Unit
- •17.6.1 Compare Output Mode and Waveform Generation
- •17.7 Modes of Operation
- •17.7.1 Normal Mode
- •17.7.2 Clear Timer on Compare Match (CTC) Mode
- •17.7.3 Fast PWM Mode
- •17.7.4 Phase Correct PWM Mode
- •17.8 Timer/Counter Timing Diagrams
- •17.9 Asynchronous Operation of the Timer/Counter
- •17.9.1 Asynchronous Operation of Timer/Counter2
- •17.10 Timer/Counter Prescaler
- •17.11 Register Description
- •17.11.1 TCCR2 – Timer/Counter Control Register
- •17.11.2 TCNT2 – Timer/Counter Register
- •17.11.3 OCR2 – Output Compare Register
- •17.11.4 ASSR – Asynchronous Status Register
- •17.11.5 TIMSK – Timer/Counter Interrupt Mask Register
- •17.11.6 TIFR – Timer/Counter Interrupt Flag Register
- •17.11.7 SFIOR – Special Function IO Register
- •18. Serial Peripheral Interface – SPI
- •18.1 Features
- •18.2 Overview
- •18.3 SS Pin Functionality
- •18.3.1 Slave Mode
- •18.3.2 Master Mode
- •18.4 Data Modes
- •18.5 Register Description
- •18.5.1 SPCR – SPI Control Register
- •18.5.2 SPSR – SPI Status Register
- •18.5.3 SPDR – SPI Data Register
- •19. USART
- •19.1 Features
- •19.2 Overview
- •19.2.1 AVR USART vs. AVR UART – Compatibility
- •19.3 Clock Generation
- •19.3.1 Internal Clock Generation – The Baud Rate Generator
- •19.3.2 Double Speed Operation (U2X)
- •19.3.3 External Clock
- •19.3.4 Synchronous Clock Operation
- •19.4 Frame Formats
- •19.4.1 Parity Bit Calculation
- •19.5 USART Initialization
- •19.6 Data Transmission – The USART Transmitter
- •19.6.1 Sending Frames with 5 to 8 Data Bits
- •19.6.2 Sending Frames with 9 Data Bits
- •19.6.3 Transmitter Flags and Interrupts
- •19.6.4 Parity Generator
- •19.6.5 Disabling the Transmitter
- •19.6.6 Data Reception – The USART Receiver
- •Receiving Frames with 5 to 8 Data Bits
- •19.6.7 Receiving Frames with 9 Data Bits
- •19.6.8 Receive Compete Flag and Interrupt
- •19.6.9 Receiver Error Flags
- •19.6.10 Parity Checker
- •19.6.11 Disabling the Receiver
- •19.7 Asynchronous Data Reception
- •19.7.1 Asynchronous Clock Recovery
- •19.7.2 Asynchronous Data Recovery
- •19.7.3 Asynchronous Operational Range
- •19.8.1 Using MPCM
- •19.9 Accessing UBRRH/UCSRC Registers
- •19.9.1 Write Access
- •19.9.2 Read Access
- •19.10 Register Description
- •19.10.1 UDR– USART I/O Data Register
- •19.10.2 UCSRA – USART Control and Status Register A
- •19.10.3 UCSRB – USART Control and Status Register B
- •19.10.4 UCSRC – USART Control and Status Register C
- •19.10.5 UBRRL and UBRRH – USART Baud Rate Registers
- •19.11 Examples of Baud Rate Setting
- •20. Two-wire Serial Interface
- •20.1 Features
- •20.2 Overview
- •20.2.1 SCL and SDA Pins
- •20.2.2 Bit Rate Generator Unit
- •20.2.3 Bus Interface Unit
- •20.2.4 Address Match Unit
- •20.2.5 Control Unit
- •20.3.1 TWI Terminology
- •20.3.2 Electrical Interconnection
- •20.4 Data Transfer and Frame Format
- •20.4.1 Transferring Bits
- •20.4.2 START and STOP Conditions
- •20.4.3 Address Packet Format
- •20.4.4 Data Packet Format
- •20.4.5 Combining Address and Data Packets into a Transmission
- •20.6 Using the TWI
- •20.6.1 Transmission Modes
- •20.6.2 Master Transmitter Mode
- •20.6.3 Master Receiver Mode
- •20.6.4 Slave Receiver Mode
- •20.6.5 Slave Transmitter Mode
- •20.6.6 Miscellaneous States
- •20.6.7 Combining Several TWI Modes
- •20.8 Register Description
- •20.8.1 TWBR – TWI Bit Rate Register
- •20.8.2 TWCR – TWI Control Register
- •20.8.3 TWI Status Register – TWSR
- •20.8.4 TWDR – TWI Data Register
- •20.8.5 TWAR – TWI (Slave) Address Register
- •21. Analog Comparator
- •21.1 Overview
- •21.2 Analog Comparator Multiplexed Input
- •21.3 Register Description
- •21.3.1 SFIOR – Special Function IO Register
- •21.3.2 ACSR – Analog Comparator Control and Status Register
- •22. Analog-to-Digital Converter
- •22.1 Features
- •22.2 Overview
- •22.3 Starting a Conversion
- •22.4 Prescaling and Conversion Timing
- •22.5 Changing Channel or Reference Selection
- •22.5.1 ADC Input Channels
- •22.5.2 ADC Voltage Reference
- •22.6 ADC Noise Canceler
- •22.6.1 Analog Input Circuitry
- •22.6.2 Analog Noise Canceling Techniques
- •22.6.3 ADC Accuracy Definitions
- •22.7 ADC Conversion Result
- •22.8 Register Description
- •22.8.1 ADMUX – ADC Multiplexer Selection Register – ADMUX
- •22.8.2 ADCSRA – ADC Control and Status Register A
- •22.8.3 ADCL and ADCH – The ADC Data Register
- •23. Boot Loader Support – Read-While-Write Self-Programming
- •23.1 Features
- •23.2 Overview
- •23.3 Application and Boot Loader Flash Sections
- •23.3.1 Application Section
- •23.3.2 BLS – Boot Loader Section
- •23.5 Boot Loader Lock Bits
- •23.6 Entering the Boot Loader Program
- •23.8.1 Performing Page Erase by SPM
- •23.8.2 Filling the Temporary Buffer (Page Loading)
- •23.8.3 Performing a Page Write
- •23.8.4 Using the SPM Interrupt
- •23.8.5 Consideration While Updating BLS
- •23.8.7 Setting the Boot Loader Lock Bits by SPM
- •23.8.8 EEPROM Write Prevents Writing to SPMCR
- •23.8.9 Reading the Fuse and Lock Bits from Software
- •23.8.10 Preventing Flash Corruption
- •23.8.11 Programming Time for Flash when using SPM
- •23.8.12 Simple Assembly Code Example for a Boot Loader
- •23.8.13 Boot Loader Parameters
- •23.9 Register Description
- •23.9.1 Store Program Memory Control Register – SPMCR
- •24. Memory Programming
- •24.1 Program And Data Memory Lock Bits
- •24.2 Fuse Bits
- •24.2.1 Latching of Fuses
- •24.3 Signature Bytes
- •24.4 Calibration Byte
- •24.5 Page Size
- •24.6 Parallel Programming Parameters, Pin Mapping, and Commands
- •24.6.1 Signal Names
- •24.7 Parallel Programming
- •24.7.1 Enter Programming Mode
- •24.7.2 Considerations for Efficient Programming
- •24.7.3 Chip Erase
- •24.7.4 Programming the Flash
- •24.7.5 Programming the EEPROM
- •24.7.6 Reading the Flash
- •24.7.7 Reading the EEPROM
- •24.7.8 Programming the Fuse Low Bits
- •24.7.9 Programming the Fuse High Bits
- •24.7.10 Programming the Lock Bits
- •24.7.11 Reading the Fuse and Lock Bits
- •24.7.12 Reading the Signature Bytes
- •24.7.13 Reading the Calibration Byte
- •24.7.14 Parallel Programming Characteristics
- •24.8 Serial Downloading
- •24.9 Serial Programming Pin Mapping
- •24.9.1 Serial Programming Algorithm
- •24.9.2 Data Polling Flash
- •24.9.3 Data Polling EEPROM
- •24.9.4 SPI Serial Programming Characteristics
- •25. Electrical Characteristics
- •25.1 Absolute Maximum Ratings*
- •25.2 DC Characteristics
- •25.3 Speed Grades
- •25.4 Clock Characteristics
- •25.4.1 External Clock Drive Waveforms
- •25.4.2 External Clock Drive
- •25.5 System and Reset Characteristics
- •25.7 SPI Timing Characteristics
- •25.8 ADC Characteristics
- •26. Typical Characteristics
- •26.1 Active Supply Current
- •26.2 Idle Supply Current
- •26.5 Standby Supply Current
- •26.7 Pin Driver Strength
- •26.8 Pin Thresholds and Hysteresis
- •26.9 Bod Thresholds and Analog Comparator Offset
- •26.10 Internal Oscillator Speed
- •26.11 Current Consumption of Peripheral Units
- •26.12 Current Consumption in Reset and Reset Pulsewidth
- •27. Register Summary
- •28. Instruction Set Summary
- •29. Ordering Information
- •30. Packaging Information
- •31. Errata
- •31.1 ATmega8A, rev. L
- •32. Datasheet Revision History
- •Table of Contents
ATmega8A
are present in the system, some of these might transmit data to the TWI, and then SR mode would be used. It is the application software that decides which modes are legal.
The following sections describe each of these modes. Possible status codes are described along with figures detailing data transmission in each of the modes. These figures contain the following abbreviations:
S: START condition
Rs: REPEATED START condition
R: Read bit (high level at SDA)
W: Write bit (low level at SDA)
A: Acknowledge bit (low level at SDA)
A: Not acknowledge bit (high level at SDA)
Data: 8-bit data byte
P: STOP condition
SLA: Slave Address
In Figure 20-12 to Figure 20-8, circles are used to indicate that the TWINT Flag is set. The numbers in the circles show the status code held in TWSR, with the prescaler bits masked to zero. At these points, actions must be taken by the application to continue or complete the TWI transfer. The TWI transfer is suspended until the TWINT Flag is cleared by software.
When the TWINT Flag is set, the status code in TWSR is used to determine the appropriate software action. For each status code, the required software action and details of the following serial transfer are given in Table 20-3 to Table 20-7. Note that the prescaler bits are masked to zero in these tables.
20.6.2Master Transmitter Mode
In the Master Transmitter mode, a number of data bytes are transmitted to a Slave Receiver (see Figure 20-11). In order to enter a Master mode, a START condition must be transmitted. The format of the following address packet determines whether Master Transmitter or Master Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered. All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero.
Figure 20-11. Data Transfer in Master Transmitter Mode
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MASTER |
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TRANSMITTER |
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RECEIVER |
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SDA
SCL
177
8159C–AVR–07/09
ATmega8A
A START condition is sent by writing the following value to TWCR:
TWCR |
TWINT |
TWEA |
TWSTA |
TWSTO |
TWWC |
TWEN |
– |
TWIE |
value |
1 |
X |
1 |
0 |
X |
1 |
0 |
X |
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TWEN must be set to enable the Two-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be written to one to clear the TWINT Flag. The TWI will then test the Two-wire Serial Bus and generate a START condition as soon as the bus becomes free. After a START condition has been transmitted, the TWINT Flag is set by hardware, and the status code in TWSR will be 0x08 (see Table 20-3). In order to enter MT mode, SLA+W must be transmitted. This is done by writing SLA+W to TWDR. Thereafter the TWINT bit should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing the following value to TWCR:
TWCR |
TWINT |
TWEA |
TWSTA |
TWSTO |
TWWC |
TWEN |
– |
TWIE |
value |
1 |
X |
0 |
0 |
X |
1 |
0 |
X |
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When SLA+W have been transmitted and an acknowledgement bit has been received, TWINT is set again and a number of status codes in TWSR are possible. Possible status codes in Master mode are 0x18, 0x20, or 0x38. The appropriate action to be taken for each of these status codes is detailed in Table 20-3.
When SLA+W has been successfully transmitted, a data packet should be transmitted. This is done by writing the data byte to TWDR. TWDR must only be written when TWINT is high. If not, the access will be discarded, and the Write Collision bit (TWWC) will be set in the TWCR Register. After updating TWDR, the TWINT bit should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing the following value to TWCR:
TWCR |
TWINT |
TWEA |
TWSTA |
TWSTO |
TWWC |
TWEN |
– |
TWIE |
value |
1 |
X |
0 |
0 |
X |
1 |
0 |
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This scheme is repeated until the last byte has been sent and the transfer is ended by generating a STOP condition or a repeated START condition. A STOP condition is generated by writing the following value to TWCR:
TWCR |
TWINT |
TWEA |
TWSTA |
TWSTO |
TWWC |
TWEN |
– |
TWIE |
value |
1 |
X |
0 |
1 |
X |
1 |
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A REPEATED START condition is generated by writing the following value to TWCR:
TWCR |
TWINT |
TWEA |
TWSTA |
TWSTO |
TWWC |
TWEN |
– |
TWIE |
value |
1 |
X |
1 |
0 |
X |
1 |
0 |
X |
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Table 20-2. After a repeated START condition (state 0x10) the Two-wire Serial Interface can access the same Slave again, or a new Slave without transmitting a STOP condition. Repeated START enables the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control of the bus:
178
8159C–AVR–07/09
ATmega8A
Table 20-3. |
Status codes for Master Transmitter Mode |
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Status Code |
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Application Software Response |
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(TWSR) |
Status of the Two-wire Serial |
To/from TWDR |
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To TWCR |
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Prescaler Bits |
Bus and Two-wire Serial Inter- |
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are 0 |
face Hardware |
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STA |
STO |
TWINT |
TWEA |
Next Action Taken by TWI Hardware |
0x08 |
A START condition has been |
Load SLA+W |
0 |
0 |
1 |
X |
SLA+W will be transmitted; |
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transmitted |
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ACK or NOT ACK will be received |
0x10 |
A repeated START condition |
Load SLA+W or |
0 |
0 |
1 |
X |
SLA+W will be transmitted; |
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has been transmitted |
Load SLA+R |
0 |
0 |
1 |
X |
ACK or NOT ACK will be received |
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SLA+R will be transmitted; |
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Logic will switch to Master Receiver mode |
0x18 |
SLA+W has been transmitted; |
Load data byte or |
0 |
0 |
1 |
X |
Data byte will be transmitted and ACK or NOT ACK will |
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ACK has been received |
No TWDR action or |
1 |
0 |
1 |
X |
be received |
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Repeated START will be transmitted |
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No TWDR action or |
0 |
1 |
1 |
X |
STOP condition will be transmitted and |
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No TWDR action |
1 |
1 |
1 |
X |
TWSTO Flag will be reset |
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STOP condition followed by a START condition will be |
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transmitted and TWSTO Flag will be reset |
0x20 |
SLA+W has been transmitted; |
Load data byte or |
0 |
0 |
1 |
X |
Data byte will be transmitted and ACK or NOT ACK will |
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NOT ACK has been received |
No TWDR action or |
1 |
0 |
1 |
X |
be received |
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Repeated START will be transmitted |
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No TWDR action or |
0 |
1 |
1 |
X |
STOP condition will be transmitted and |
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No TWDR action |
1 |
1 |
1 |
X |
TWSTO Flag will be reset |
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STOP condition followed by a START condition will be |
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transmitted and TWSTO Flag will be reset |
0x28 |
Data byte has been transmitted; |
Load data byte or |
0 |
0 |
1 |
X |
Data byte will be transmitted and ACK or NOT ACK will |
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ACK has been received |
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be received |
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No TWDR action or |
1 |
0 |
1 |
Repeated START will be transmitted |
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No TWDR action or |
0 |
1 |
1 |
X |
STOP condition will be transmitted and |
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X |
TWSTO Flag will be reset |
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No TWDR action |
1 |
1 |
STOP condition followed by a START condition will be |
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transmitted and TWSTO Flag will be reset |
0x30 |
Data byte has been transmitted; |
Load data byte or |
0 |
0 |
1 |
X |
Data byte will be transmitted and ACK or NOT ACK will |
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NOT ACK has been received |
No TWDR action or |
1 |
0 |
1 |
X |
be received |
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Repeated START will be transmitted |
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No TWDR action or |
0 |
1 |
1 |
X |
STOP condition will be transmitted and |
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No TWDR action |
1 |
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X |
TWSTO Flag will be reset |
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STOP condition followed by a START condition will be |
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transmitted and TWSTO Flag will be reset |
0x38 |
Arbitration lost in SLA+W or data |
No TWDR action or |
0 |
0 |
1 |
X |
Two-wire Serial Bus will be released and not addressed |
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No TWDR action |
1 |
0 |
1 |
X |
Slave mode entered |
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A START condition will be transmitted when the bus be- |
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comes free |
179
8159C–AVR–07/09
ATmega8A
Figure 20-12. Formats and States in the Master Transmitter Mode
MT
Successfull |
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S |
SLA |
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A |
DATA |
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P |
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transmission |
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to a slave |
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receiver |
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$08 |
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$18 |
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$28 |
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Next transfer |
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RS |
SLA |
W |
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started with a |
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repeated start |
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condition |
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$10 |
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Not acknowledge |
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R |
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P |
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received after the |
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A |
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slave address |
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$20
MR
Not acknowledge
received after a data A P byte
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$30 |
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Arbitration lost in slave |
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Other master |
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address or data byte |
A or A |
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continues |
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A or A |
continues |
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$38 |
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Arbitration lost and |
A |
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addressed as slave |
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To corresponding |
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$78 |
$B0 |
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states in slave mode |
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From master to slave |
DATA |
A |
Any number of data bytes |
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and their associated acknowledge bits |
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From slave to master |
n |
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This number (contained in TWSR) corresponds |
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to a defined state of the Two-Wire Serial Bus. The |
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prescaler bits are zero or masked to zero |
20.6.3Master Receiver Mode
In the Master Receiver mode, a number of data bytes are received from a Slave Transmitter (see Figure 20-13). In order to enter a Master mode, a START condition must be transmitted. The format of the following address packet determines whether Master Transmitter or Master Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered. All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero.
180
8159C–AVR–07/09
ATmega8A
Figure 20-13. Data Transfer in Master Receiver Mode
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VCC |
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Device 1 |
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Device 2 |
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Device 3 |
........ |
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Device n |
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R1 |
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MASTER |
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SLAVE |
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RECEIVER |
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TRANSMITTER |
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SDA
SCL
A START condition is sent by writing the following value to TWCR:
TWCR |
TWINT |
TWEA |
TWSTA |
TWSTO |
TWWC |
TWEN |
– |
TWIE |
value |
1 |
X |
1 |
0 |
X |
1 |
0 |
X |
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TWEN must be written to one to enable the Two-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be set to clear the TWINT Flag. The TWI will then test the Two-wire Serial Bus and generate a START condition as soon as the bus becomes free. After a START condition has been transmitted, the TWINT Flag is set by hardware, and the status code in TWSR will be 0x08 (See Table 20-3). In order to enter MR mode, SLA+R must be transmitted. This is done by writing SLA+R to TWDR. Thereafter the TWINT bit should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing the following value to TWCR:
TWCR |
TWINT |
TWEA |
TWSTA |
TWSTO |
TWWC |
TWEN |
– |
TWIE |
value |
1 |
X |
0 |
0 |
X |
1 |
0 |
X |
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When SLA+R have been transmitted and an acknowledgement bit has been received, TWINT is set again and a number of status codes in TWSR are possible. Possible status codes in Master mode are 0x38, 0x40, or 0x48. The appropriate action to be taken for each of these status codes is detailed in Table 20-4. Received data can be read from the TWDR Register when the TWINT Flag is set high by hardware. This scheme is repeated until the last byte has been received. After the last byte has been received, the MR should inform the ST by sending a NACK after the last received data byte. The transfer is ended by generating a STOP condition or a repeated START condition. A STOP condition is generated by writing the following value to TWCR:
TWCR |
TWINT |
TWEA |
TWSTA |
TWSTO |
TWWC |
TWEN |
– |
TWIE |
value |
1 |
X |
0 |
1 |
X |
1 |
0 |
X |
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A REPEATED START condition is generated by writing the following value to TWCR:
TWCR |
TWINT |
TWEA |
TWSTA |
TWSTO |
TWWC |
TWEN |
– |
TWIE |
value |
1 |
X |
1 |
0 |
X |
1 |
0 |
X |
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After a repeated START condition (state 0x10) the Two-wire Serial Interface can access the same Slave again, or a new Slave without transmitting a STOP condition. Repeated START enables the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control over the bus.
181
8159C–AVR–07/09
ATmega8A
Table 20-4. |
Status codes for Master Receiver Mode |
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Status Code |
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Application Software Response |
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(TWSR) |
Status of the Two-wire Serial |
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To TWCR |
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Prescaler Bits |
Bus and Two-wire Serial Inter- |
To/from TWDR |
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are 0 |
face Hardware |
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STA |
STO |
TWINT |
TWEA |
Next Action Taken by TWI Hardware |
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0x08 |
A START condition has been |
Load SLA+R |
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0 |
0 |
1 |
X |
SLA+R will be transmitted |
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transmitted |
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ACK or NOT ACK will be received |
0x10 |
A repeated START condition |
Load SLA+R or |
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0 |
0 |
1 |
X |
SLA+R will be transmitted |
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has been transmitted |
Load SLA+W |
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0 |
0 |
1 |
X |
ACK or NOT ACK will be received |
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SLA+W will be transmitted |
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Logic will switch to Master Transmitter mode |
0x38 |
Arbitration lost in SLA+R or NOT |
No TWDR action or |
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0 |
0 |
1 |
X |
Two-wire Serial Bus will be released and not addressed |
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ACK bit |
No TWDR action |
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1 |
0 |
1 |
X |
Slave mode will be entered |
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A START condition will be transmitted when the bus |
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becomes free |
0x40 |
SLA+R has been transmitted; |
No TWDR action or |
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0 |
0 |
1 |
0 |
Data byte will be received and NOT ACK will be |
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ACK has been received |
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returned |
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No TWDR action |
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0 |
0 |
1 |
1 |
Data byte will be received and ACK will be returned |
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0x48 |
SLA+R has been transmitted; |
No TWDR action or |
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1 |
0 |
1 |
X |
Repeated START will be transmitted |
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NOT ACK has been received |
No TWDR action or |
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0 |
1 |
1 |
X |
STOP condition will be transmitted and TWSTO Flag will |
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No TWDR action |
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1 |
1 |
1 |
X |
be reset |
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STOP condition followed by a START condition will be |
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transmitted and TWSTO Flag will be reset |
0x50 |
Data byte has been received; |
Read data byte or |
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0 |
0 |
1 |
0 |
Data byte will be received and NOT ACK will be |
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ACK has been returned |
Read data byte |
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0 |
0 |
1 |
1 |
returned |
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Data byte will be received and ACK will be returned |
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0x58 |
Data byte has been received; |
Read data byte or |
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1 |
0 |
1 |
X |
Repeated START will be transmitted |
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NOT ACK has been returned |
Read data byte or |
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0 |
1 |
1 |
X |
STOP condition will be transmitted and TWSTO Flag will |
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1 |
1 |
1 |
X |
be reset |
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Read data byte |
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STOP condition followed by a START condition will be |
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transmitted and TWSTO Flag will be reset |
182
8159C–AVR–07/09