ATmega8A

Figure 24-2. Programming the EEPROM Waveforms

							K
	A	G	B	C	E	B	C	E	L
DATA	0x11	ADDR. HIGH	ADDR. LOW	DATA	XX	ADDR. LOW	DATA	XX

XA1

XA0

BS1

XTAL1

WR

RDY/BSY

RESET +12V

OE

PAGEL

BS2

24.7.6Reading the Flash

The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” on page 232 for details on Command and Address loading):

1.A: Load Command “0000 0010”.

2.G: Load Address High byte (0x00 - 0xFF).

3.B: Load Address Low byte (0x00 - 0xFF).

4.Set OE to “0”, and BS1 to “0”. The Flash word Low byte can now be read at DATA.

5.Set BS1 to “1”. The Flash word High byte can now be read at DATA.

6.Set OE to “1”.

24.7.7Reading the EEPROM

The algorithm for reading the EEPROM memory is as follows (refer to “Programming the Flash” on page 232 for details on Command and Address loading):

1.A: Load Command “0000 0011”.

2.G: Load Address High byte (0x00 - 0xFF).

3.B: Load Address Low byte (0x00 - 0xFF).

4.Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA.

5.Set OE to “1”.

24.7.8Programming the Fuse Low Bits

The algorithm for programming the Fuse Low bits is as follows (refer to “Programming the Flash” on page 232 for details on Command and Data loading):

1.A: Load Command “0100 0000”.

2.C: Load Data Low byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

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3.Set BS1 and BS2 to “0”.

4.Give WR a negative pulse and wait for RDY/BSY to go high.

24.7.9Programming the Fuse High Bits

The algorithm for programming the Fuse high bits is as follows (refer to “Programming the Flash” on page 232 for details on Command and Data loading):

1.A: Load Command “0100 0000”.

2.C: Load Data Low byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3.Set BS1 to “1” and BS2 to “0”. This selects high data byte.

4.Give WR a negative pulse and wait for RDY/BSY to go high.

5.Set BS1 to “0”. This selects low data byte.

24.7.10Programming the Lock Bits

The algorithm for programming the Lock Bits is as follows (refer to “Programming the Flash” on page 232 for details on Command and Data loading):

1.A: Load Command “0010 0000”.

2.C: Load Data Low byte. Bit n = “0” programs the Lock bit.

3.Give WR a negative pulse and wait for RDY/BSY to go high. The Lock Bits can only be cleared by executing Chip Erase.

24.7.11Reading the Fuse and Lock Bits

The algorithm for reading the Fuse and Lock Bits is as follows (refer to “Programming the Flash” on page 232 for details on Command loading):

1.A: Load Command “0000 0100”.

2.Set OE to “0”, BS2 to “0”, and BS1 to “0”. The status of the Fuse Low bits can now be read at DATA (“0” means programmed).

3.Set OE to “0”, BS2 to “1”, and BS1 to “1”. The status of the Fuse High bits can now be read at DATA (“0” means programmed).

4.Set OE to “0”, BS2 to “0”, and BS1 to “1”. The status of the Lock Bits can now be read at DATA (“0” means programmed).

5.Set OE to “1”.

Figure 24-3. Mapping Between BS1, BS2 and the Fuseand Lock Bits During Read

Fuse low byte 0

DATA

Lock bits				0						1
Fuse high byte					1
										BS1
		BS2

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24.7.12Reading the Signature Bytes

The algorithm for reading the Signature bytes is as follows (refer to “Programming the Flash” on page 232 for details on Command and Address loading):

1.A: Load Command “0000 1000”.

2.B: Load Address Low byte (0x00 - 0x02).

3.Set OE to “0”, and BS1 to “0”. The selected Signature byte can now be read at DATA.

4.Set OE to “1”.

24.7.13Reading the Calibration Byte

The algorithm for reading the Calibration bytes is as follows (refer to “Programming the Flash” on page 232 for details on Command and Address loading):

1.A: Load Command “0000 1000”.

2.B: Load Address Low byte, (0x00 - 0x03).

3.Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.

4.Set OE to “1”.

24.7.14Parallel Programming Characteristics

Figure 24-4. Parallel Programming Timing, Including some General Timing Requirements

	tXLWL
XTAL1	tXHXL
tDVXH	tXLDX
Data & Contol
(DATA, XA0/1, BS1, BS2)
tBVPH	tPLBX	t BVWL	tWLBX
PAGEL	tPHPL
			tWL WH
WR	tPLWL		WLRL
RDY/BSY
			tWLRH

Figure 24-5. Parallel Programming Timing, Loading Sequence with Timing Requirements(1)

LOAD ADDRESS

LOAD DATA

LOAD DATA LOAD DATA

LOAD ADDRESS

(LOW BYTE)

(LOW BYTE)

(HIGH BYTE)

(LOW BYTE)

t XLXH

tXLPH

tPLXH

XTAL1

BS1

PAGEL

DATA

ADDR0 (Low Byte)

DATA (Low Byte)

DATA (High Byte)

ADDR1 (Low Byte)

XA0

XA1

Note:

1.

The timing requirements shown in Figure 24-4 (i.e., tDVXH, tXHXL, and tXLDX) also apply to load-

ing operation.

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Figure 24-6. Parallel Programming Timing, Reading Sequence (within the same Page) with Timing Requirements(1)

LOAD ADDRESS

READ DATA

READ DATA

LOAD ADDRESS

(LOW BYTE)

(LOW BYTE)

(HIGH BYTE)

(LOW BYTE)

tXLOL

XTAL1

BS1

tBVDV

tOLDV

OE

tOHDZ

ADDR1 (Low Byte)

DATA

ADDR0 (Low Byte)

DATA (Low Byte)

DATA (High Byte)

XA0

XA1

Note: 1.

The timing requirements shown in Figure 24-4 (i.e., tDVXH, tXHXL, and tXLDX) also apply to read-

ing operation.

Table 24-13. Parallel Programming Characteristics, VCC = 5V ± 10%

Symbol

Parameter

Min

Typ

Max

Units

VPP

Programming Enable Voltage

11.5

12.5

V

IPP

Programming Enable Current

250

μA

tDVXH

Data and Control Valid before XTAL1 High

67

ns

tXLXH

XTAL1 Low to XTAL1 High

200

ns

tXHXL

XTAL1 Pulse Width High

150

ns

tXLDX

Data and Control Hold after XTAL1 Low

67

ns

tXLWL

XTAL1 Low to

Low

0

ns

WR

tXLPH

XTAL1 Low to PAGEL high

0

ns

tPLXH

PAGEL low to XTAL1 high

150

ns

tBVPH

BS1 Valid before PAGEL High

67

ns

tPHPL

PAGEL Pulse Width High

150

ns

tPLBX

BS1 Hold after PAGEL Low

67

ns

tWLBX

BS2/1 Hold after

Low

67

ns

WR

tPLWL

PAGEL Low to

Low

67

ns

WR

tBVWL

BS1 Valid to

Low

67

ns

WR

tWLWH

Pulse Width Low

150

ns

WR

tWLRL

Low

0

1

μs

WR

Low to RDY/BSY

tWLRH

High(1)

3.7

4.5

ms

WR

Low to RDY/BSY

tWLRH_CE

High for Chip Erase(2)

7.5

9

ms

WR

Low to RDY/BSY

tXLOL

XTAL1 Low to

Low

0

ns

OE

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