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23.8.3Performing a Page Write

To execute page write, set up the address in the Z-pointer, write “X0000101” to SPMCR and execute SPM within four clock cycles after writing SPMCR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to zero during this operation.

•Page Write to the RWW section: The NRWW section can be read during the page write.

•Page Write to the NRWW section: The CPU is halted during the operation.

23.8.4Using the SPM Interrupt

If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the SPMEN bit in SPMCR is cleared. This means that the interrupt can be used instead of polling the SPMCR Register in software. When using the SPM interrupt, the Interrupt Vectors should be moved to the BLS section to avoid that an interrupt is accessing the RWW section when it is blocked for reading. How to move the interrupts is described in “Interrupts” on page 45.

23.8.5Consideration While Updating BLS

Special care must be taken if the user allows the Boot Loader section to be updated by leaving Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself can corrupt the entire Boot Loader, and further software updates might be impossible. If it is not necessary to change the Boot Loader software itself, it is recommended to program the Boot Lock bit11 to protect the Boot Loader software from any internal software changes.

23.8.6Prevent Reading the RWW Section During Self-Programming

During Self-Programming (either page erase or page write), the RWW section is always blocked for reading. The user software itself must prevent that this section is addressed during the self programming operation. The RWWSB in the SPMCR will be set as long as the RWW section is busy. During Self-Programming the Interrupt Vector table should be moved to the BLS as described in “Interrupts” on page 45, or the interrupts must be disabled. Before addressing the RWW section after the programming is completed, the user software must clear the RWWSB by writing the RWWSRE. See “Simple Assembly Code Example for a Boot Loader” on page 221 for an example.

23.8.7Setting the Boot Loader Lock Bits by SPM

To set the Boot Loader Lock Bits, write the desired data to R0, write “X0001001” to SPMCR and execute SPM within four clock cycles after writing SPMCR. The only accessible Lock Bits are the Boot Lock Bits that may prevent the Application and Boot Loader section from any software update by the MCU.

Bit	7	6	5	4	3	2	1	0
R0	1	1	BLB12	BLB11	BLB02	BLB01	1	1

See Table 23-2 and Table 23-3 for how the different settings of the Boot Loader Bits affect the Flash access.

If bits 5:2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an SPM instruction is executed within four cycles after BLBSET and SPMEN are set in SPMCR. The Z-pointer is don’t care during this operation, but for future compatibility it is recommended to load the Z-pointer with 0x0001 (same as used for reading the Lock Bits). For future compatibility It is also recommended to set bits 7, 6, 1, and 0 in R0 to “1” when writing the Lock Bits. When programming the Lock Bits the entire Flash can be read during the operation.

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23.8.8EEPROM Write Prevents Writing to SPMCR

Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock Bits from software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit (EEWE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCR Register.

23.8.9Reading the Fuse and Lock Bits from Software

It is possible to read both the Fuse and Lock Bits from software. To read the Lock Bits, load the Z-pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCR. When an LPM instruction is executed within three CPU cycles after the BLBSET and SPMEN bits are set in SPMCR, the value of the Lock Bits will be loaded in the destination register. The BLBSET and SPMEN bits will auto-clear upon completion of reading the Lock Bits or if no LPM instruction is executed within three CPU cycles or no SPM instruction is executed within four CPU cycles. When BLBSET and SPMEN are cleared, LPM will work as described in the Instruction set Manual.

Bit		7	6	5	4	3	2	1	0
Rd		–	–	BLB12	BLB11	BLB02	BLB01	LB2	LB1

The algorithm for reading the Fuse Low bits is similar to the one described above for reading the Lock Bits. To read the Fuse Low bits, load the Z-pointer with 0x0000 and set the BLBSET and SPMEN bits in SPMCR. When an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCR, the value of the Fuse Low bits (FLB) will be loaded in the destination register as shown below. Refer to Table 24-4 on page 228 for a detailed description and mapping of the fuse low bits.

Bit	7	6	5	4	3	2	1	0
Rd	FLB7	FLB6	FLB5	FLB4	FLB3	FLB2	FLB1	FLB0

Similarly, when reading the Fuse High bits, load 0x0003 in the Z-pointer. When an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCR, the value of the Fuse High bits (FHB) will be loaded in the destination register as shown below. Refer to Table 24-3 on page 227 for detailed description and mapping of the fuse high bits.

Bit	7	6	5	4	3	2	1	0
Rd	FHB7	FHB6	FHB5	FHB4	FHB3	FHB2	FHB1	FHB0

Fuse and Lock Bits that are programmed, will be read as zero. Fuse and Lock Bits that are unprogrammed, will be read as one.

23.8.10Preventing Flash Corruption

During periods of low VCC, the Flash program can be corrupted because the supply voltage is too low for the CPU and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions should be applied.

A Flash program corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions is too low.

Flash corruption can easily be avoided by following these design recommendations (one is sufficient):

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1.If there is no need for a Boot Loader update in the system, program the Boot Loader Lock Bits to prevent any Boot Loader software updates.

2.Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD) if the operating

voltage matches the detection level. If not, an external low VCC Reset Protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.

3.Keep the AVR core in Power-down sleep mode during periods of low VCC. This will prevent the CPU from attempting to decode and execute instructions, effectively protecting the SPMCR Register and thus the Flash from unintentional writes.

23.8.11Programming Time for Flash when using SPM

The calibrated RC Oscillator is used to time Flash accesses. Table 23-5 shows the typical programming time for Flash accesses from the CPU.

Table 23-5.	SPM Programming Time (1)
Symbol			Min Programming Time	Max Programming Time
Flash write (page erase, page write, and			3.7 ms	4.5 ms
write Lock Bits by SPM)

1.Minimum and maximum programming time is per individual operation.

23.8.12Simple Assembly Code Example for a Boot Loader

;-the routine writes one page of data from RAM to Flash

;the first data location in RAM is pointed to by the Y pointer

;the first data location in Flash is pointed to by the Z-pointer ;-error handling is not included

;-the routine must be placed inside the boot space

;(at least the Do_spm sub routine). Only code inside NRWW section can

;be read during self-programming (page erase and page write).

;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24),

;loophi (r25), spmcrval (r20)

;storing and restoring of registers is not included in the routine

;register usage can be optimized at the expense of code size

;-It	is assumed that either the interrupt table is moved to the Boot
; loader section or that the interrupts are disabled.
.equ PAGESIZEB = PAGESIZE*2		;PAGESIZEB is page size in BYTES, not words
.org SMALLBOOTSTART
Write_page:
; page erase
ldi	spmcrval, (1<<PGERS) | (1<<SPMEN)
rcallDo_spm
; re-enable the RWW section
ldi	spmcrval, (1<<RWWSRE) | (1<<SPMEN)
rcallDo_spm
; transfer data from RAM to Flash page buffer
ldi	looplo, low(PAGESIZEB)	;init loop variable
ldi	loophi, high(PAGESIZEB)	;not required for PAGESIZEB<=256
Wrloop:
ld	r0, Y+
ld	r1, Y+
ldi	spmcrval, (1<<SPMEN)

rcallDo_spm

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adiw	ZH:ZL, 2
sbiw	loophi:looplo, 2	;use subi for PAGESIZEB<=256
brne	Wrloop
; execute page write
subi	ZL, low(PAGESIZEB)	;restore pointer
sbci	ZH, high(PAGESIZEB)	;not required for PAGESIZEB<=256
ldi	spmcrval, (1<<PGWRT) | (1<<SPMEN)
rcallDo_spm
; re-enable the RWW section
ldi	spmcrval, (1<<RWWSRE) | (1<<SPMEN)
rcallDo_spm
; read back and check, optional
ldi	looplo, low(PAGESIZEB)	;init loop variable
ldi	loophi, high(PAGESIZEB)	;not required for PAGESIZEB<=256
subi	YL, low(PAGESIZEB)	;restore pointer
sbci	YH, high(PAGESIZEB)
Rdloop:
lpm	r0, Z+
ld	r1, Y+
cpse	r0, r1
rjmp	Error
sbiw	loophi:looplo, 1	;use subi for PAGESIZEB<=256
brne	Rdloop

;return to RWW section

;verify that RWW section is safe to read Return:

in temp1, SPMCR

sbrs	temp1, RWWSB	; If RWWSB is set, the RWW section is not
ready yet
ret
; re-enable the RWW section
ldi	spmcrval, (1<<RWWSRE) | (1<<SPMEN)
rcallDo_spm
rjmp	Return

Do_spm:

;check for previous SPM complete Wait_spm:

in temp1, SPMCR sbrc temp1, SPMEN rjmp Wait_spm

;input: spmcrval determines SPM action

;disable interrupts if enabled, store status in temp2, SREG

cli

;check that no EEPROM write access is present Wait_ee:

sbic EECR, EEWE rjmp Wait_ee

;SPM timed sequence

out SPMCR, spmcrval spm

; restore SREG (to enable interrupts if originally enabled) out SREG, temp2

ret

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