- •Features
- •1. Pin Configurations
- •2. Overview
- •2.1 Block Diagram
- •2.2 Pin Descriptions
- •2.2.3 Port B (PB7:PB0) – XTAL1/XTAL2/TOSC1/TOSC2
- •2.2.4 Port C (PC5:PC0)
- •2.2.5 PC6/RESET
- •2.2.6 Port D (PD7:PD0)
- •2.2.7 RESET
- •2.2.9 AREF
- •2.2.10 ADC7:6 (TQFP and QFN/MLF Package Only)
- •3. Resources
- •4. Data Retention
- •5. About Code Examples
- •6. AVR CPU Core
- •6.1 Overview
- •6.2 Arithmetic Logic Unit – ALU
- •6.3 Status Register
- •6.3.1 SREG – The AVR Status Register
- •6.4 General Purpose Register File
- •6.5 Stack Pointer
- •6.5.1 SPH and SPL – Stack Pointer High and Low Register
- •6.6 Instruction Execution Timing
- •6.7 Reset and Interrupt Handling
- •6.7.1 Interrupt Response Time
- •7. AVR Memories
- •7.1 Overview
- •7.3 SRAM Data Memory
- •7.3.1 Data Memory Access Times
- •7.4 EEPROM Data Memory
- •7.4.1 EEPROM Read/Write Access
- •7.5 I/O Memory
- •7.6 Register Description
- •7.6.1 EEARH and EEARL – The EEPROM Address Register
- •7.6.2 EEDR – The EEPROM Data Register
- •7.6.3 EECR – The EEPROM Control Register
- •7.6.5 Preventing EEPROM Corruption
- •8. System Clock and Clock Options
- •8.1 Clock Systems and their Distribution
- •8.2 Clock Sources
- •8.3 Crystal Oscillator
- •8.5 External RC Oscillator
- •8.6 Calibrated Internal RC Oscillator
- •8.7 External Clock
- •8.8 Timer/Counter Oscillator
- •8.9 Register Description
- •8.9.1 OSCCAL – Oscillator Calibration Register
- •9. Power Management and Sleep Modes
- •9.1 Sleep Modes
- •9.2 Idle Mode
- •9.3 ADC Noise Reduction Mode
- •9.6 Standby Mode
- •9.7 Minimizing Power Consumption
- •9.7.2 Analog Comparator
- •9.7.4 Internal Voltage Reference
- •9.7.5 Watchdog Timer
- •9.7.6 Port Pins
- •9.8 Register Description
- •9.8.1 MCUCR – MCU Control Register
- •10. System Control and Reset
- •10.1 Resetting the AVR
- •10.2 Reset Sources
- •10.2.2 External Reset
- •10.2.4 Watchdog Reset
- •10.3 Internal Voltage Reference
- •10.4 Watchdog Timer
- •10.5 Timed Sequences for Changing the Configuration of the Watchdog Timer
- •10.5.1 Safety Level 1 (WDTON Fuse Unprogrammed)
- •10.5.2 Safety Level 2 (WDTON Fuse Programmed)
- •10.6 Register Description
- •10.6.1 MCUCSR – MCU Control and Status Register
- •10.6.2 WDTCR – Watchdog Timer Control Register
- •11. Interrupts
- •11.1 Interrupt Vectors in ATmega8A
- •11.1.1 Moving Interrupts Between Application and Boot Space
- •11.2 Register Description
- •11.2.1 GICR – General Interrupt Control Register
- •12. I/O Ports
- •12.1 Overview
- •12.2 Ports as General Digital I/O
- •12.2.1 Configuring the Pin
- •12.2.2 Reading the Pin Value
- •12.2.3 Digital Input Enable and Sleep Modes
- •12.2.4 Unconnected pins
- •12.3 Alternate Port Functions
- •12.3.1 SFIOR – Special Function IO Register
- •12.3.2 Alternate Functions of Port B
- •12.3.3 Alternate Functions of Port C
- •12.3.4 Alternate Functions of Port D
- •12.4 Register Description
- •12.4.1 PORTB – The Port B Data Register
- •12.4.2 DDRB – The Port B Data Direction Register
- •12.4.3 PINB – The Port B Input Pins Address
- •12.4.4 PORTC – The Port C Data Register
- •12.4.5 DDRC – The Port C Data Direction Register
- •12.4.6 PINC – The Port C Input Pins Address
- •12.4.7 PORTD – The Port D Data Register
- •12.4.8 DDRD – The Port D Data Direction Register
- •12.4.9 PIND – The Port D Input Pins Address
- •13. External Interrupts
- •13.1 Register Description
- •13.1.1 MCUCR – MCU Control Register
- •13.1.2 GICR – General Interrupt Control Register
- •13.1.3 GIFR – General Interrupt Flag Register
- •14. 8-bit Timer/Counter0
- •14.1 Features
- •14.2 Overview
- •14.2.1 Registers
- •14.2.2 Definitions
- •14.3 Timer/Counter Clock Sources
- •14.4 Counter Unit
- •14.5 Operation
- •14.6 Timer/Counter Timing Diagrams
- •14.7 Register Description
- •14.7.1 TCCR0 – Timer/Counter Control Register
- •14.7.2 TCNT0 – Timer/Counter Register
- •14.7.3 TIMSK – Timer/Counter Interrupt Mask Register
- •14.7.4 TIFR – Timer/Counter Interrupt Flag Register
- •15. Timer/Counter0 and Timer/Counter1 Prescalers
- •15.1 Overview
- •15.2 Internal Clock Source
- •15.3 Prescaler Reset
- •15.4 External Clock Source
- •15.5 Register Description
- •15.5.1 SFIOR – Special Function IO Register
- •16. 16-bit Timer/Counter1
- •16.1 Features
- •16.2 Overview
- •16.2.1 Registers
- •16.2.2 Definitions
- •16.2.3 Compatibility
- •16.3.1 Reusing the Temporary High Byte Register
- •16.4 Timer/Counter Clock Sources
- •16.5 Counter Unit
- •16.6 Input Capture Unit
- •16.6.1 Input Capture Pin Source
- •16.6.2 Noise Canceler
- •16.6.3 Using the Input Capture Unit
- •16.7 Output Compare Units
- •16.7.1 Force Output Compare
- •16.7.2 Compare Match Blocking by TCNT1 Write
- •16.7.3 Using the Output Compare Unit
- •16.8 Compare Match Output Unit
- •16.8.1 Compare Output Mode and Waveform Generation
- •16.9 Modes of Operation
- •16.9.1 Normal Mode
- •16.9.2 Clear Timer on Compare Match (CTC) Mode
- •16.9.3 Fast PWM Mode
- •16.9.4 Phase Correct PWM Mode
- •16.9.5 Phase and Frequency Correct PWM Mode
- •16.10 Timer/Counter Timing Diagrams
- •16.11 Register Description
- •16.11.1 TCCR1A – Timer/Counter 1 Control Register A
- •16.11.2 TCCR1B – Timer/Counter 1 Control Register B
- •16.11.3 TCNT1H and TCNT1L – Timer/Counter 1
- •16.11.4 OCR1AH and OCR1AL– Output Compare Register 1 A
- •16.11.5 OCR1BH and OCR1BL – Output Compare Register 1 B
- •16.11.6 ICR1H and ICR1L – Input Capture Register 1
- •17. 8-bit Timer/Counter2 with PWM and Asynchronous Operation
- •17.1 Features
- •17.2 Overview
- •17.2.1 Registers
- •17.2.2 Definitions
- •17.3 Timer/Counter Clock Sources
- •17.4 Counter Unit
- •17.5 Output Compare Unit
- •17.5.1 Force Output Compare
- •17.5.2 Compare Match Blocking by TCNT2 Write
- •17.5.3 Using the Output Compare Unit
- •17.6 Compare Match Output Unit
- •17.6.1 Compare Output Mode and Waveform Generation
- •17.7 Modes of Operation
- •17.7.1 Normal Mode
- •17.7.2 Clear Timer on Compare Match (CTC) Mode
- •17.7.3 Fast PWM Mode
- •17.7.4 Phase Correct PWM Mode
- •17.8 Timer/Counter Timing Diagrams
- •17.9 Asynchronous Operation of the Timer/Counter
- •17.9.1 Asynchronous Operation of Timer/Counter2
- •17.10 Timer/Counter Prescaler
- •17.11 Register Description
- •17.11.1 TCCR2 – Timer/Counter Control Register
- •17.11.2 TCNT2 – Timer/Counter Register
- •17.11.3 OCR2 – Output Compare Register
- •17.11.4 ASSR – Asynchronous Status Register
- •17.11.5 TIMSK – Timer/Counter Interrupt Mask Register
- •17.11.6 TIFR – Timer/Counter Interrupt Flag Register
- •17.11.7 SFIOR – Special Function IO Register
- •18. Serial Peripheral Interface – SPI
- •18.1 Features
- •18.2 Overview
- •18.3 SS Pin Functionality
- •18.3.1 Slave Mode
- •18.3.2 Master Mode
- •18.4 Data Modes
- •18.5 Register Description
- •18.5.1 SPCR – SPI Control Register
- •18.5.2 SPSR – SPI Status Register
- •18.5.3 SPDR – SPI Data Register
- •19. USART
- •19.1 Features
- •19.2 Overview
- •19.2.1 AVR USART vs. AVR UART – Compatibility
- •19.3 Clock Generation
- •19.3.1 Internal Clock Generation – The Baud Rate Generator
- •19.3.2 Double Speed Operation (U2X)
- •19.3.3 External Clock
- •19.3.4 Synchronous Clock Operation
- •19.4 Frame Formats
- •19.4.1 Parity Bit Calculation
- •19.5 USART Initialization
- •19.6 Data Transmission – The USART Transmitter
- •19.6.1 Sending Frames with 5 to 8 Data Bits
- •19.6.2 Sending Frames with 9 Data Bits
- •19.6.3 Transmitter Flags and Interrupts
- •19.6.4 Parity Generator
- •19.6.5 Disabling the Transmitter
- •19.6.6 Data Reception – The USART Receiver
- •Receiving Frames with 5 to 8 Data Bits
- •19.6.7 Receiving Frames with 9 Data Bits
- •19.6.8 Receive Compete Flag and Interrupt
- •19.6.9 Receiver Error Flags
- •19.6.10 Parity Checker
- •19.6.11 Disabling the Receiver
- •19.7 Asynchronous Data Reception
- •19.7.1 Asynchronous Clock Recovery
- •19.7.2 Asynchronous Data Recovery
- •19.7.3 Asynchronous Operational Range
- •19.8.1 Using MPCM
- •19.9 Accessing UBRRH/UCSRC Registers
- •19.9.1 Write Access
- •19.9.2 Read Access
- •19.10 Register Description
- •19.10.1 UDR– USART I/O Data Register
- •19.10.2 UCSRA – USART Control and Status Register A
- •19.10.3 UCSRB – USART Control and Status Register B
- •19.10.4 UCSRC – USART Control and Status Register C
- •19.10.5 UBRRL and UBRRH – USART Baud Rate Registers
- •19.11 Examples of Baud Rate Setting
- •20. Two-wire Serial Interface
- •20.1 Features
- •20.2 Overview
- •20.2.1 SCL and SDA Pins
- •20.2.2 Bit Rate Generator Unit
- •20.2.3 Bus Interface Unit
- •20.2.4 Address Match Unit
- •20.2.5 Control Unit
- •20.3.1 TWI Terminology
- •20.3.2 Electrical Interconnection
- •20.4 Data Transfer and Frame Format
- •20.4.1 Transferring Bits
- •20.4.2 START and STOP Conditions
- •20.4.3 Address Packet Format
- •20.4.4 Data Packet Format
- •20.4.5 Combining Address and Data Packets into a Transmission
- •20.6 Using the TWI
- •20.6.1 Transmission Modes
- •20.6.2 Master Transmitter Mode
- •20.6.3 Master Receiver Mode
- •20.6.4 Slave Receiver Mode
- •20.6.5 Slave Transmitter Mode
- •20.6.6 Miscellaneous States
- •20.6.7 Combining Several TWI Modes
- •20.8 Register Description
- •20.8.1 TWBR – TWI Bit Rate Register
- •20.8.2 TWCR – TWI Control Register
- •20.8.3 TWI Status Register – TWSR
- •20.8.4 TWDR – TWI Data Register
- •20.8.5 TWAR – TWI (Slave) Address Register
- •21. Analog Comparator
- •21.1 Overview
- •21.2 Analog Comparator Multiplexed Input
- •21.3 Register Description
- •21.3.1 SFIOR – Special Function IO Register
- •21.3.2 ACSR – Analog Comparator Control and Status Register
- •22. Analog-to-Digital Converter
- •22.1 Features
- •22.2 Overview
- •22.3 Starting a Conversion
- •22.4 Prescaling and Conversion Timing
- •22.5 Changing Channel or Reference Selection
- •22.5.1 ADC Input Channels
- •22.5.2 ADC Voltage Reference
- •22.6 ADC Noise Canceler
- •22.6.1 Analog Input Circuitry
- •22.6.2 Analog Noise Canceling Techniques
- •22.6.3 ADC Accuracy Definitions
- •22.7 ADC Conversion Result
- •22.8 Register Description
- •22.8.1 ADMUX – ADC Multiplexer Selection Register – ADMUX
- •22.8.2 ADCSRA – ADC Control and Status Register A
- •22.8.3 ADCL and ADCH – The ADC Data Register
- •23. Boot Loader Support – Read-While-Write Self-Programming
- •23.1 Features
- •23.2 Overview
- •23.3 Application and Boot Loader Flash Sections
- •23.3.1 Application Section
- •23.3.2 BLS – Boot Loader Section
- •23.5 Boot Loader Lock Bits
- •23.6 Entering the Boot Loader Program
- •23.8.1 Performing Page Erase by SPM
- •23.8.2 Filling the Temporary Buffer (Page Loading)
- •23.8.3 Performing a Page Write
- •23.8.4 Using the SPM Interrupt
- •23.8.5 Consideration While Updating BLS
- •23.8.7 Setting the Boot Loader Lock Bits by SPM
- •23.8.8 EEPROM Write Prevents Writing to SPMCR
- •23.8.9 Reading the Fuse and Lock Bits from Software
- •23.8.10 Preventing Flash Corruption
- •23.8.11 Programming Time for Flash when using SPM
- •23.8.12 Simple Assembly Code Example for a Boot Loader
- •23.8.13 Boot Loader Parameters
- •23.9 Register Description
- •23.9.1 Store Program Memory Control Register – SPMCR
- •24. Memory Programming
- •24.1 Program And Data Memory Lock Bits
- •24.2 Fuse Bits
- •24.2.1 Latching of Fuses
- •24.3 Signature Bytes
- •24.4 Calibration Byte
- •24.5 Page Size
- •24.6 Parallel Programming Parameters, Pin Mapping, and Commands
- •24.6.1 Signal Names
- •24.7 Parallel Programming
- •24.7.1 Enter Programming Mode
- •24.7.2 Considerations for Efficient Programming
- •24.7.3 Chip Erase
- •24.7.4 Programming the Flash
- •24.7.5 Programming the EEPROM
- •24.7.6 Reading the Flash
- •24.7.7 Reading the EEPROM
- •24.7.8 Programming the Fuse Low Bits
- •24.7.9 Programming the Fuse High Bits
- •24.7.10 Programming the Lock Bits
- •24.7.11 Reading the Fuse and Lock Bits
- •24.7.12 Reading the Signature Bytes
- •24.7.13 Reading the Calibration Byte
- •24.7.14 Parallel Programming Characteristics
- •24.8 Serial Downloading
- •24.9 Serial Programming Pin Mapping
- •24.9.1 Serial Programming Algorithm
- •24.9.2 Data Polling Flash
- •24.9.3 Data Polling EEPROM
- •24.9.4 SPI Serial Programming Characteristics
- •25. Electrical Characteristics
- •25.1 Absolute Maximum Ratings*
- •25.2 DC Characteristics
- •25.3 Speed Grades
- •25.4 Clock Characteristics
- •25.4.1 External Clock Drive Waveforms
- •25.4.2 External Clock Drive
- •25.5 System and Reset Characteristics
- •25.7 SPI Timing Characteristics
- •25.8 ADC Characteristics
- •26. Typical Characteristics
- •26.1 Active Supply Current
- •26.2 Idle Supply Current
- •26.5 Standby Supply Current
- •26.7 Pin Driver Strength
- •26.8 Pin Thresholds and Hysteresis
- •26.9 Bod Thresholds and Analog Comparator Offset
- •26.10 Internal Oscillator Speed
- •26.11 Current Consumption of Peripheral Units
- •26.12 Current Consumption in Reset and Reset Pulsewidth
- •27. Register Summary
- •28. Instruction Set Summary
- •29. Ordering Information
- •30. Packaging Information
- •31. Errata
- •31.1 ATmega8A, rev. L
- •32. Datasheet Revision History
- •Table of Contents
ATmega8A
27. Register Summary
Address |
Name |
Bit 7 |
Bit 6 |
Bit 5 |
|
Bit 4 |
Bit 3 |
|
Bit 2 |
Bit 1 |
Bit 0 |
Page |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0x3F (0x5F) |
SREG |
I |
T |
H |
|
S |
V |
|
N |
Z |
C |
8 |
|
0x3E (0x5E) |
SPH |
– |
– |
– |
|
– |
– |
|
SP10 |
SP9 |
SP8 |
11 |
|
0x3D (0x5D) |
SPL |
SP7 |
SP6 |
SP5 |
|
SP4 |
SP3 |
|
SP2 |
SP1 |
SP0 |
11 |
|
0x3C (0x5C) |
Reserved |
|
|
|
|
|
|
|
|
|
|
|
|
0x3B (0x5B) |
GICR |
INT1 |
INT0 |
– |
|
– |
– |
|
– |
IVSEL |
IVCE |
48, 68 |
|
0x3A (0x5A) |
GIFR |
INTF1 |
INTF0 |
– |
|
– |
– |
|
– |
– |
– |
69 |
|
0x39 |
(0x59) |
TIMSK |
OCIE2 |
TOIE2 |
TICIE1 |
|
OCIE1A |
OCIE1B |
|
TOIE1 |
– |
TOIE0 |
73, 104, 124 |
0x38 |
(0x58) |
TIFR |
OCF2 |
TOV2 |
ICF1 |
|
OCF1A |
OCF1B |
|
TOV1 |
– |
TOV0 |
74, 104, 104 |
0x37 |
(0x57) |
SPMCR |
SPMIE |
RWWSB |
– |
|
RWWSRE |
BLBSET |
|
PGWRT |
PGERS |
SPMEN |
224 |
0x36 |
(0x56) |
TWCR |
TWINT |
TWEA |
TWSTA |
|
TWSTO |
TWWC |
|
TWEN |
– |
TWIE |
191 |
0x35 |
(0x55) |
MCUCR |
SE |
SM2 |
SM1 |
|
SM0 |
ISC11 |
|
ISC10 |
ISC01 |
ISC00 |
36, 67 |
0x34 |
(0x54) |
MCUCSR |
– |
– |
– |
|
– |
WDRF |
|
BORF |
EXTRF |
PORF |
43 |
0x33 |
(0x53) |
TCCR0 |
– |
– |
– |
|
– |
– |
|
CS02 |
CS01 |
CS00 |
73 |
0x32 |
(0x52) |
TCNT0 |
|
|
|
|
Timer/Counter0 (8 Bits) |
|
|
|
73 |
||
0x31 |
(0x51) |
OSCCAL |
|
|
|
|
Oscillator Calibration Register |
|
|
|
31 |
||
0x30 |
(0x50) |
SFIOR |
– |
– |
– |
|
– |
ACME |
|
PUD |
PSR2 |
PSR10 |
57, 77, 125, 196 |
0x2F |
(0x4F) |
TCCR1A |
COM1A1 |
COM1A0 |
COM1B1 |
|
COM1B0 |
FOC1A |
|
FOC1B |
WGM11 |
WGM10 |
99 |
0x2E |
(0x4E) |
TCCR1B |
ICNC1 |
ICES1 |
– |
|
WGM13 |
WGM12 |
|
CS12 |
CS11 |
CS10 |
101 |
0x2D |
(0x4D) |
TCNT1H |
|
|
Timer/Counter1 – Counter Register High byte |
|
|
102 |
|||||
0x2C |
(0x4C) |
TCNT1L |
|
|
Timer/Counter1 – Counter Register Low byte |
|
|
102 |
|||||
0x2B |
(0x4B) |
OCR1AH |
|
|
Timer/Counter1 – Output Compare Register A High byte |
|
|
103 |
|||||
0x2A |
(0x4A) |
OCR1AL |
|
|
Timer/Counter1 – Output Compare Register A Low byte |
|
|
103 |
|||||
0x29 |
(0x49) |
OCR1BH |
|
|
Timer/Counter1 – Output Compare Register B High byte |
|
|
103 |
|||||
0x28 |
(0x48) |
OCR1BL |
|
|
Timer/Counter1 – Output Compare Register B Low byte |
|
|
103 |
|||||
0x27 |
(0x47) |
ICR1H |
|
|
Timer/Counter1 – Input Capture Register High byte |
|
|
103 |
|||||
0x26 |
(0x46) |
ICR1L |
|
|
Timer/Counter1 – Input Capture Register Low byte |
|
|
103 |
|||||
0x25 |
(0x45) |
TCCR2 |
FOC2 |
WGM20 |
COM21 |
|
COM20 |
WGM21 |
|
CS22 |
CS21 |
CS20 |
121 |
0x24 |
(0x44) |
TCNT2 |
|
|
|
|
Timer/Counter2 (8 Bits) |
|
|
|
123 |
||
0x23 |
(0x43) |
OCR2 |
|
|
|
Timer/Counter2 Output Compare Register |
|
|
123 |
||||
0x22 |
(0x42) |
ASSR |
– |
– |
– |
|
– |
AS2 |
|
TCN2UB |
OCR2UB |
TCR2UB |
123 |
0x21 |
(0x41) |
WDTCR |
– |
– |
– |
|
WDCE |
WDE |
|
WDP2 |
WDP1 |
WDP0 |
43 |
0x20(1) |
(0x40)(1) |
UBRRH |
URSEL |
– |
– |
|
– |
|
|
UBRR[11:8] |
|
160 |
|
UCSRC |
URSEL |
UMSEL |
UPM1 |
|
UPM0 |
USBS |
|
UCSZ1 |
UCSZ0 |
UCPOL |
159 |
||
|
|
|
|
||||||||||
0x1F (0x3F) |
EEARH |
– |
– |
– |
|
– |
– |
|
– |
– |
EEAR8 |
19 |
|
0x1E (0x3E) |
EEARL |
EEAR7 |
EEAR6 |
EEAR5 |
|
EEAR4 |
EEAR3 |
|
EEAR2 |
EEAR1 |
EEAR0 |
19 |
|
0x1D (0x3D) |
EEDR |
|
|
|
|
EEPROM Data Register |
|
|
|
19 |
|||
0x1C (0x3C) |
EECR |
– |
– |
– |
|
– |
EERIE |
|
EEMWE |
EEWE |
EERE |
19 |
|
0x1B (0x3B) |
Reserved |
|
|
|
|
|
|
|
|
|
|
|
|
0x1A (0x3A) |
Reserved |
|
|
|
|
|
|
|
|
|
|
|
|
0x19 |
(0x39) |
Reserved |
|
|
|
|
|
|
|
|
|
|
|
0x18 |
(0x38) |
PORTB |
PORTB7 |
PORTB6 |
PORTB5 |
|
PORTB4 |
PORTB3 |
|
PORTB2 |
PORTB1 |
PORTB0 |
65 |
0x17 |
(0x37) |
DDRB |
DDB7 |
DDB6 |
DDB5 |
|
DDB4 |
DDB3 |
|
DDB2 |
DDB1 |
DDB0 |
65 |
0x16 |
(0x36) |
PINB |
PINB7 |
PINB6 |
PINB5 |
|
PINB4 |
PINB3 |
|
PINB2 |
PINB1 |
PINB0 |
65 |
0x15 |
(0x35) |
PORTC |
– |
PORTC6 |
PORTC5 |
|
PORTC4 |
PORTC3 |
|
PORTC2 |
PORTC1 |
PORTC0 |
65 |
0x14 |
(0x34) |
DDRC |
– |
DDC6 |
DDC5 |
|
DDC4 |
DDC3 |
|
DDC2 |
DDC1 |
DDC0 |
65 |
0x13 |
(0x33) |
PINC |
– |
PINC6 |
PINC5 |
|
PINC4 |
PINC3 |
|
PINC2 |
PINC1 |
PINC0 |
65 |
0x12 |
(0x32) |
PORTD |
PORTD7 |
PORTD6 |
PORTD5 |
|
PORTD4 |
PORTD3 |
|
PORTD2 |
PORTD1 |
PORTD0 |
65 |
0x11 |
(0x31) |
DDRD |
DDD7 |
DDD6 |
DDD5 |
|
DDD4 |
DDD3 |
|
DDD2 |
DDD1 |
DDD0 |
65 |
0x10 |
(0x30) |
PIND |
PIND7 |
PIND6 |
PIND5 |
|
PIND4 |
PIND3 |
|
PIND2 |
PIND1 |
PIND0 |
66 |
0x0F (0x2F) |
SPDR |
|
|
|
|
SPI Data Register |
|
|
|
135 |
|||
0x0E (0x2E) |
SPSR |
SPIF |
WCOL |
– |
|
– |
– |
|
– |
– |
SPI2X |
134 |
|
0x0D (0x2D) |
SPCR |
SPIE |
SPE |
DORD |
|
MSTR |
CPOL |
|
CPHA |
SPR1 |
SPR0 |
133 |
|
0x0C (0x2C) |
UDR |
|
|
|
|
USART I/O Data Register |
|
|
|
156 |
|||
0x0B (0x2B) |
UCSRA |
RXC |
TXC |
UDRE |
|
FE |
DOR |
|
PE |
U2X |
MPCM |
157 |
|
0x0A (0x2A) |
UCSRB |
RXCIE |
TXCIE |
UDRIE |
|
RXEN |
TXEN |
|
UCSZ2 |
RXB8 |
TXB8 |
158 |
|
0x09 |
(0x29) |
UBRRL |
|
|
|
USART Baud Rate Register Low byte |
|
|
|
160 |
|||
0x08 |
(0x28) |
ACSR |
ACD |
ACBG |
ACO |
|
ACI |
ACIE |
|
ACIC |
ACIS1 |
ACIS0 |
196 |
0x07 |
(0x27) |
ADMUX |
REFS1 |
REFS0 |
ADLAR |
|
– |
MUX3 |
|
MUX2 |
MUX1 |
MUX0 |
208 |
0x06 |
(0x26) |
ADCSRA |
ADEN |
ADSC |
ADFR |
|
ADIF |
ADIE |
|
ADPS2 |
ADPS1 |
ADPS0 |
209 |
0x05 |
(0x25) |
ADCH |
|
|
|
|
ADC Data Register High byte |
|
|
|
210 |
||
0x04 |
(0x24) |
ADCL |
|
|
|
|
ADC Data Register Low byte |
|
|
|
210 |
||
0x03 |
(0x23) |
TWDR |
|
|
|
Two-wire Serial Interface Data Register |
|
|
|
193 |
|||
0x02 |
(0x22) |
TWAR |
TWA6 |
TWA5 |
TWA4 |
|
TWA3 |
TWA2 |
|
TWA1 |
TWA0 |
TWGCE |
194 |
289
8159C–AVR–07/09
ATmega8A
27. Register Summary (Continued)
Address |
|
Name |
Bit 7 |
Bit 6 |
Bit 5 |
|
Bit 4 |
Bit 3 |
|
Bit 2 |
|
Bit 1 |
Bit 0 |
Page |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0x01 (0x21) |
|
TWSR |
TWS7 |
TWS6 |
TWS5 |
|
TWS4 |
TWS3 |
|
– |
|
TWPS1 |
TWPS0 |
193 |
0x00 (0x20) |
|
TWBR |
|
|
|
Two-wire Serial Interface Bit Rate Register |
|
|
|
|
191 |
|||
Note: 1. |
Refer to the USART description for details on how to access UBRRH and UCSRC. |
|
|
|
||||||||||
2.For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.
3.Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
290
8159C–AVR–07/09
ATmega8A
28. Instruction Set Summary
Mnemonics |
Operands |
|
Description |
Operation |
Flags |
#Clocks |
|
|
|
|
|
|
|
ARITHMETIC AND LOGIC INSTRUCTIONS |
|
|
|
|
||
ADD |
Rd, Rr |
|
Add two Registers |
Rd ← Rd + Rr |
Z,C,N,V,H |
1 |
ADC |
Rd, Rr |
|
Add with Carry two Registers |
Rd ← Rd + Rr + C |
Z,C,N,V,H |
1 |
ADIW |
Rdl,K |
|
Add Immediate to Word |
Rdh:Rdl ← Rdh:Rdl + K |
Z,C,N,V,S |
2 |
SUB |
Rd, Rr |
|
Subtract two Registers |
Rd ← Rd - Rr |
Z,C,N,V,H |
1 |
SUBI |
Rd, K |
|
Subtract Constant from Register |
Rd ← Rd - K |
Z,C,N,V,H |
1 |
SBC |
Rd, Rr |
|
Subtract with Carry two Registers |
Rd ← Rd - Rr - C |
Z,C,N,V,H |
1 |
SBCI |
Rd, K |
|
Subtract with Carry Constant from Reg. |
Rd ← Rd - K - C |
Z,C,N,V,H |
1 |
SBIW |
Rdl,K |
|
Subtract Immediate from Word |
Rdh:Rdl ← Rdh:Rdl - K |
Z,C,N,V,S |
2 |
AND |
Rd, Rr |
|
Logical AND Registers |
Rd ← Rd • Rr |
Z,N,V |
1 |
ANDI |
Rd, K |
|
Logical AND Register and Constant |
Rd ← Rd • K |
Z,N,V |
1 |
OR |
Rd, Rr |
|
Logical OR Registers |
Rd ← Rd v Rr |
Z,N,V |
1 |
ORI |
Rd, K |
|
Logical OR Register and Constant |
Rd ← Rd v K |
Z,N,V |
1 |
EOR |
Rd, Rr |
|
Exclusive OR Registers |
Rd ← Rd Rr |
Z,N,V |
1 |
COM |
Rd |
|
One’s Complement |
Rd ← 0xFF − Rd |
Z,C,N,V |
1 |
NEG |
Rd |
|
Two’s Complement |
Rd ← 0x00 − Rd |
Z,C,N,V,H |
1 |
SBR |
Rd,K |
|
Set Bit(s) in Register |
Rd ← Rd v K |
Z,N,V |
1 |
CBR |
Rd,K |
|
Clear Bit(s) in Register |
Rd ← Rd • (0xFF - K) |
Z,N,V |
1 |
INC |
Rd |
|
Increment |
Rd ← Rd + 1 |
Z,N,V |
1 |
DEC |
Rd |
|
Decrement |
Rd ← Rd − 1 |
Z,N,V |
1 |
TST |
Rd |
|
Test for Zero or Minus |
Rd ← Rd • Rd |
Z,N,V |
1 |
CLR |
Rd |
|
Clear Register |
Rd ← Rd Rd |
Z,N,V |
1 |
SER |
Rd |
|
Set Register |
Rd ← 0xFF |
None |
1 |
MUL |
Rd, Rr |
|
Multiply Unsigned |
R1:R0 ← Rd x Rr |
Z,C |
2 |
MULS |
Rd, Rr |
|
Multiply Signed |
R1:R0 ← Rd x Rr |
Z,C |
2 |
MULSU |
Rd, Rr |
|
Multiply Signed with Unsigned |
R1:R0 ← Rd x Rr |
Z,C |
2 |
FMUL |
Rd, Rr |
|
Fractional Multiply Unsigned |
R1:R0 ← (Rd x Rr) << 1 |
Z,C |
2 |
FMULS |
Rd, Rr |
|
Fractional Multiply Signed |
R1:R0 ← (Rd x Rr) << 1 |
Z,C |
2 |
FMULSU |
Rd, Rr |
|
Fractional Multiply Signed with Unsigned |
R1:R0 ← (Rd x Rr) << 1 |
Z,C |
2 |
BRANCH INSTRUCTIONS |
|
|
|
|
||
RJMP |
k |
|
Relative Jump |
PC ← PC + k + 1 |
None |
2 |
IJMP |
|
|
Indirect Jump to (Z) |
PC ← Z |
None |
2 |
RCALL |
k |
|
Relative Subroutine Call |
PC ← PC + k + 1 |
None |
3 |
ICALL |
|
|
Indirect Call to (Z) |
PC ← Z |
None |
3 |
RET |
|
|
Subroutine Return |
PC ← STACK |
None |
4 |
RETI |
|
|
Interrupt Return |
PC ← STACK |
I |
4 |
CPSE |
Rd,Rr |
|
Compare, Skip if Equal |
if (Rd = Rr) PC ← PC + 2 or 3 |
None |
1 / 2 / 3 |
CP |
Rd,Rr |
|
Compare |
Rd − Rr |
Z, N,V,C,H |
1 |
CPC |
Rd,Rr |
|
Compare with Carry |
Rd − Rr − C |
Z, N,V,C,H |
1 |
CPI |
Rd,K |
|
Compare Register with Immediate |
Rd − K |
Z, N,V,C,H |
1 |
SBRC |
Rr, b |
|
Skip if Bit in Register Cleared |
if (Rr(b)=0) PC ← PC + 2 or 3 |
None |
1 / 2 / 3 |
SBRS |
Rr, b |
|
Skip if Bit in Register is Set |
if (Rr(b)=1) PC ← PC + 2 or 3 |
None |
1 / 2 / 3 |
SBIC |
P, b |
|
Skip if Bit in I/O Register Cleared |
if (P(b)=0) PC ← PC + 2 or 3 |
None |
1 / 2 / 3 |
SBIS |
P, b |
|
Skip if Bit in I/O Register is Set |
if (P(b)=1) PC ← PC + 2 or 3 |
None |
1 / 2 / 3 |
BRBS |
s, k |
|
Branch if Status Flag Set |
if (SREG(s) = 1) then PC←PC+k + 1 |
None |
1 / 2 |
BRBC |
s, k |
|
Branch if Status Flag Cleared |
if (SREG(s) = 0) then PC←PC+k + 1 |
None |
1 / 2 |
BREQ |
k |
|
Branch if Equal |
if (Z = 1) then PC ← PC + k + 1 |
None |
1 / 2 |
BRNE |
k |
|
Branch if Not Equal |
if (Z = 0) then PC ← PC + k + 1 |
None |
1 / 2 |
BRCS |
k |
|
Branch if Carry Set |
if (C = 1) then PC ← PC + k + 1 |
None |
1 / 2 |
BRCC |
k |
|
Branch if Carry Cleared |
if (C = 0) then PC ← PC + k + 1 |
None |
1 / 2 |
BRSH |
k |
|
Branch if Same or Higher |
if (C = 0) then PC ← PC + k + 1 |
None |
1 / 2 |
BRLO |
k |
|
Branch if Lower |
if (C = 1) then PC ← PC + k + 1 |
None |
1 / 2 |
BRMI |
k |
|
Branch if Minus |
if (N = 1) then PC ← PC + k + 1 |
None |
1 / 2 |
BRPL |
k |
|
Branch if Plus |
if (N = 0) then PC ← PC + k + 1 |
None |
1 / 2 |
BRGE |
k |
|
Branch if Greater or Equal, Signed |
if (N V= 0) then PC ← PC + k + 1 |
None |
1 / 2 |
BRLT |
k |
|
Branch if Less Than Zero, Signed |
if (N V= 1) then PC ← PC + k + 1 |
None |
1 / 2 |
BRHS |
k |
|
Branch if Half Carry Flag Set |
if (H = 1) then PC ← PC + k + 1 |
None |
1 / 2 |
BRHC |
k |
|
Branch if Half Carry Flag Cleared |
if (H = 0) then PC ← PC + k + 1 |
None |
1 / 2 |
BRTS |
k |
|
Branch if T Flag Set |
if (T = 1) then PC ← PC + k + 1 |
None |
1 / 2 |
BRTC |
k |
|
Branch if T Flag Cleared |
if (T = 0) then PC ← PC + k + 1 |
None |
1 / 2 |
BRVS |
k |
|
Branch if Overflow Flag is Set |
if (V = 1) then PC ← PC + k + 1 |
None |
1 / 2 |
BRVC |
k |
|
Branch if Overflow Flag is Cleared |
if (V = 0) then PC ← PC + k + 1 |
None |
1 / 2 |
Mnemonics |
Operands |
|
Description |
Operation |
Flags |
#Clocks |
|
|
|
|
|
|
|
291
8159C–AVR–07/09
ATmega8A
28. Instruction Set Summary (Continued)
BRIE |
k |
Branch if Interrupt Enabled |
if ( I = 1) then PC ← PC + k + 1 |
None |
1 / 2 |
BRID |
k |
Branch if Interrupt Disabled |
if ( I = 0) then PC ← PC + k + 1 |
None |
1 / 2 |
DATA TRANSFER INSTRUCTIONS |
|
|
|
|
|
MOV |
Rd, Rr |
Move Between Registers |
Rd ← Rr |
None |
1 |
MOVW |
Rd, Rr |
Copy Register Word |
Rd+1:Rd ← Rr+1:Rr |
None |
1 |
LDI |
Rd, K |
Load Immediate |
Rd ← K |
None |
1 |
LD |
Rd, X |
Load Indirect |
Rd ← (X) |
None |
2 |
LD |
Rd, X+ |
Load Indirect and Post-Inc. |
Rd ← (X), X ← X + 1 |
None |
2 |
LD |
Rd, - X |
Load Indirect and Pre-Dec. |
X ← X - 1, Rd ← (X) |
None |
2 |
LD |
Rd, Y |
Load Indirect |
Rd ← (Y) |
None |
2 |
LD |
Rd, Y+ |
Load Indirect and Post-Inc. |
Rd ← (Y), Y ← Y + 1 |
None |
2 |
LD |
Rd, - Y |
Load Indirect and Pre-Dec. |
Y ← Y - 1, Rd ← (Y) |
None |
2 |
LDD |
Rd,Y+q |
Load Indirect with Displacement |
Rd ← (Y + q) |
None |
2 |
LD |
Rd, Z |
Load Indirect |
Rd ← (Z) |
None |
2 |
LD |
Rd, Z+ |
Load Indirect and Post-Inc. |
Rd ← (Z), Z ← Z+1 |
None |
2 |
LD |
Rd, -Z |
Load Indirect and Pre-Dec. |
Z ← Z - 1, Rd ← (Z) |
None |
2 |
LDD |
Rd, Z+q |
Load Indirect with Displacement |
Rd ← (Z + q) |
None |
2 |
LDS |
Rd, k |
Load Direct from SRAM |
Rd ← (k) |
None |
2 |
ST |
X, Rr |
Store Indirect |
(X) ← Rr |
None |
2 |
ST |
X+, Rr |
Store Indirect and Post-Inc. |
(X) ← Rr, X ← X + 1 |
None |
2 |
ST |
- X, Rr |
Store Indirect and Pre-Dec. |
X ← X - 1, (X) ← Rr |
None |
2 |
ST |
Y, Rr |
Store Indirect |
(Y) ← Rr |
None |
2 |
ST |
Y+, Rr |
Store Indirect and Post-Inc. |
(Y) ← Rr, Y ← Y + 1 |
None |
2 |
ST |
- Y, Rr |
Store Indirect and Pre-Dec. |
Y ← Y - 1, (Y) ← Rr |
None |
2 |
STD |
Y+q,Rr |
Store Indirect with Displacement |
(Y + q) ← Rr |
None |
2 |
ST |
Z, Rr |
Store Indirect |
(Z) ← Rr |
None |
2 |
ST |
Z+, Rr |
Store Indirect and Post-Inc. |
(Z) ← Rr, Z ← Z + 1 |
None |
2 |
ST |
-Z, Rr |
Store Indirect and Pre-Dec. |
Z ← Z - 1, (Z) ← Rr |
None |
2 |
STD |
Z+q,Rr |
Store Indirect with Displacement |
(Z + q) ← Rr |
None |
2 |
STS |
k, Rr |
Store Direct to SRAM |
(k) ← Rr |
None |
2 |
LPM |
|
Load Program Memory |
R0 ← (Z) |
None |
3 |
LPM |
Rd, Z |
Load Program Memory |
Rd ← (Z) |
None |
3 |
LPM |
Rd, Z+ |
Load Program Memory and Post-Inc |
Rd ← (Z), Z ← Z+1 |
None |
3 |
SPM |
|
Store Program Memory |
(Z) ← R1:R0 |
None |
- |
IN |
Rd, P |
In Port |
Rd ← P |
None |
1 |
OUT |
P, Rr |
Out Port |
P ← Rr |
None |
1 |
PUSH |
Rr |
Push Register on Stack |
STACK ← Rr |
None |
2 |
POP |
Rd |
Pop Register from Stack |
Rd ← STACK |
None |
2 |
BIT AND BIT-TEST INSTRUCTIONS |
|
|
|
|
|
SBI |
P,b |
Set Bit in I/O Register |
I/O(P,b) ← 1 |
None |
2 |
CBI |
P,b |
Clear Bit in I/O Register |
I/O(P,b) ← 0 |
None |
2 |
LSL |
Rd |
Logical Shift Left |
Rd(n+1) ← Rd(n), Rd(0) ← 0 |
Z,C,N,V |
1 |
LSR |
Rd |
Logical Shift Right |
Rd(n) ← Rd(n+1), Rd(7) ← 0 |
Z,C,N,V |
1 |
ROL |
Rd |
Rotate Left Through Carry |
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) |
Z,C,N,V |
1 |
ROR |
Rd |
Rotate Right Through Carry |
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) |
Z,C,N,V |
1 |
ASR |
Rd |
Arithmetic Shift Right |
Rd(n) ← Rd(n+1), n=0:6 |
Z,C,N,V |
1 |
SWAP |
Rd |
Swap Nibbles |
Rd(3:0)←Rd(7:4),Rd(7:4)←Rd(3:0) |
None |
1 |
BSET |
s |
Flag Set |
SREG(s) ← 1 |
SREG(s) |
1 |
BCLR |
s |
Flag Clear |
SREG(s) ← 0 |
SREG(s) |
1 |
BST |
Rr, b |
Bit Store from Register to T |
T ← Rr(b) |
T |
1 |
BLD |
Rd, b |
Bit load from T to Register |
Rd(b) ← T |
None |
1 |
SEC |
|
Set Carry |
C ← 1 |
C |
1 |
CLC |
|
Clear Carry |
C ← 0 |
C |
1 |
SEN |
|
Set Negative Flag |
N ← 1 |
N |
1 |
CLN |
|
Clear Negative Flag |
N ← 0 |
N |
1 |
SEZ |
|
Set Zero Flag |
Z ← 1 |
Z |
1 |
CLZ |
|
Clear Zero Flag |
Z ← 0 |
Z |
1 |
SEI |
|
Global Interrupt Enable |
I ← 1 |
I |
1 |
CLI |
|
Global Interrupt Disable |
I ← 0 |
I |
1 |
SES |
|
Set Signed Test Flag |
S ← 1 |
S |
1 |
CLS |
|
Clear Signed Test Flag |
S ← 0 |
S |
1 |
SEV |
|
Set Twos Complement Overflow. |
V ← 1 |
V |
1 |
CLV |
|
Clear Twos Complement Overflow |
V ← 0 |
V |
1 |
SET |
|
Set T in SREG |
T ← 1 |
T |
1 |
Mnemonics |
Operands |
Description |
Operation |
Flags |
#Clocks |
|
|
|
|
|
|
292
8159C–AVR–07/09
ATmega8A
28. Instruction Set Summary (Continued)
CLT |
|
Clear T in SREG |
T ← 0 |
T |
1 |
SEH |
|
Set Half Carry Flag in SREG |
H ← 1 |
H |
1 |
CLH |
|
Clear Half Carry Flag in SREG |
H ← 0 |
H |
1 |
MCU CONTROL |
INSTRUCTIONS |
|
|
|
|
NOP |
|
No Operation |
|
None |
1 |
SLEEP |
|
Sleep |
(see specific descr. for Sleep function) |
None |
1 |
WDR |
|
Watchdog Reset |
(see specific descr. for WDR/timer) |
None |
1 |
293
8159C–AVR–07/09