C8051F060/1/2/3/4/5/6/7
			Рисунок 1.3. Структурная схема C8051F064/066
VDD										P0	P0.0
VDD
VDD	Digital Power				8		UART0			Drv
DGND											P0.7
DGND	Analog Power						UART1
DGND
AV+					0	SFR Bus	SMBus	C		P1	P1.0
AGND
							SPI Bus	R		Drv	P1.7
TCK					5			O
	JTAG	Boundary Scan						S
TMS							PCA	S
	Logic	Debug HW
TDI					1			B		P2	P2.0
TDO						FLASH	Timers 0,	A
			Reset							Drv
/RST						Memory	1, 2,3,4	R			P2.7
MONEN	VDD Monitor	WDT				64k byte	P0, P1, P2,
						(C8051F064)				P3	P3.0
XTAL1					C		P3 Latches
	External Oscillator					32k byte				Drv	P3.7
XTAL2	Circuit		System Clock			(C8051F066)
	Trimmed Internal				o
	Oscillator
					r	256 byte			+	P2.6
						RAM		CP0
VREF	VREF								-	P2.7
					e			CP1	+	P2.2
									-	P2.3
								CP2	+	P2.4
						4kbyte RAM			-	P2.5
AVDD
AGND
AV+
AGND
VREF0
VRGND0
AIN0		ADC0	A		External Data Memory Bus
AIN0G		1Msps	D
		(16-Bit)	C					P4 Latch
			0				Bus Control			P4	P4.5
VBGAP0
			D					Ctrl Latch		DRV	P4.6
CNVSTR0			A								P4.7
			T			EMIF
AV+				+				P5 Latch			P5.0
			A		D	Control	Address Bus			P5
AGND			Σ		I	DMA		Addr[15:8]		DRV	P5.7
VREF1					F	Interface
VRGND1			A	-	F			P6 Latch		P6	P6.0
			D
			C					Addr[7:0]		DRV	P6.7
AIN1		ADC1	1
AIN1G		1Msps	D					P7 Latch			P7.0
		(16-Bit)					Data Bus			P7
			A
			T					Data Latch		DRV	P7.7
VBGAP1			A
CNVSTR1

23

Ред. 1.2

C8051F060/1/2/3/4/5/6/7

Рисунок 1.4. Структурная схема C8051F065/067

VDD
VDD
VDD	Digital Power		8		UART0
DGND
DGND	Analog Power				UART1
DGND
AV+			0	SFR Bus	SMBus
AGND
					SPI Bus
TCK	JTAG	Boundary Scan	5
TMS					PCA
	Logic	Debug HW
TDI			1
TDO		Reset		FLASH	Timers 0,
/RST				Memory	1, 2,3,4

MONEN	VDD Monitor	WDT				64k byte	P0, P1, P2,
						(C8051F065)
XTAL1					C	32k byte	P3 Latches
	External Oscillator
XTAL2	Circuit		System Clock			(C8051F067)
	Trimmed Internal				o
	Oscillator
					r	256 byte
VREF	VREF					RAM
					e
						4kbyte RAM
AVDD
AGND
AV+
AGND
VREF0
VRGND0
AIN0		ADC0	A		External Data Memory Bus
AIN0G		1Msps	D
		(16-Bit)	C
			0
VBGAP0			D
CNVSTR0			A
			T				EMIF
AV+			A	+
					D	DMA	Control
AGND			Σ		I
VREF1					F
VRGND1			A	-	F	Interface
			D
			C
AIN1		ADC1	1
AIN1G		1Msps	D
		(16-Bit)	A
			T
VBGAP1			A
CNVSTR1

		P0	P0.0
		Drv	P0.7
	C	P1	P1.0
	R	Drv	P1.7
	O
	S
	S
	B	P2	P2.0
	A
		Drv
	R		P2.7
		P3
		Drv
	CP0	+	P2.6
			P2.7
		-
	CP1	+	P2.2
			P2.3
		-
	CP2	+	P2.4
			P2.5
		-

	P4 Latch			P4
	Ctrl Latch			DRV
	P5 Latch			P5
				DRV
	Addr[15:8]
	P6 Latch			P6
				DRV
	Addr[7:0]
	P7 Latch			P7
Data Latch				DRV

Ред. 1.2

24