- •Features
- •Pin Configurations
- •Overview
- •Block Diagram
- •Disclaimer
- •Pin Descriptions
- •Port C (PC5..PC0)
- •PC6/RESET
- •Port D (PD7..PD0)
- •RESET
- •AVCC
- •AREF
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •SRAM Data Memory
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •I/O Memory
- •Clock Systems and their Distribution
- •CPU Clock – clkCPU
- •I/O Clock – clkI/O
- •Flash Clock – clkFLASH
- •ADC Clock – clkADC
- •Clock Sources
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Timer/Counter Oscillator
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Standby Mode
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watchdog Timer
- •Interrupts
- •I/O Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Unconnected pins
- •Alternate Port Functions
- •Alternate Functions of Port B
- •Alternate Functions of Port C
- •Alternate Functions of Port D
- •Register Description for I/O Ports
- •External Interrupts
- •8-bit Timer/Counter0
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Operation
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •16-bit Timer/Counter1
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Trigger Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •8-bit Timer/Counter2 with PWM and Asynchronous Operation
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Timer/Counter Prescaler
- •SS Pin Functionality
- •Slave Mode
- •Master Mode
- •SPI Control Register – SPCR
- •SPI Status Register – SPSR
- •SPI Data Register – SPDR
- •Data Modes
- •USART
- •Overview
- •AVR USART vs. AVR UART – Compatibility
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Sending Frames with 9 Data Bits
- •Parity Generator
- •Disabling the Transmitter
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Write Access
- •Read Access
- •Two-wire Serial Interface
- •Features
- •TWI Terminology
- •Electrical Interconnection
- •Transferring Bits
- •START and STOP Conditions
- •Address Packet Format
- •Data Packet Format
- •Overview of the TWI Module
- •SCL and SDA Pins
- •Bit Rate Generator Unit
- •Bus Interface Unit
- •Address Match Unit
- •Control Unit
- •TWI Register Description
- •TWI Bit Rate Register – TWBR
- •TWI Control Register – TWCR
- •TWI Status Register – TWSR
- •TWI Data Register – TWDR
- •Using the TWI
- •Transmission Modes
- •Master Transmitter Mode
- •Master Receiver Mode
- •Slave Receiver Mode
- •Slave Transmitter Mode
- •Miscellaneous States
- •Analog Comparator
- •Analog Comparator Multiplexed Input
- •Features
- •Starting a Conversion
- •Changing Channel or Reference Selection
- •ADC Input Channels
- •ADC Voltage Reference
- •ADC Noise Canceler
- •Analog Input Circuitry
- •ADC Accuracy Definitions
- •ADC Conversion Result
- •The ADC Data Register – ADCL and ADCH
- •ADLAR = 0
- •ADLAR = 1
- •Boot Loader Features
- •Application Section
- •BLS – Boot Loader Section
- •Boot Loader Lock Bits
- •Performing a Page Write
- •Using the SPM Interrupt
- •Setting the Boot Loader Lock Bits by SPM
- •Reading the Fuse and Lock Bits from Software
- •Preventing Flash Corruption
- •Simple Assembly Code Example for a Boot Loader
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •Two-wire Serial Interface Characteristics
- •ADC Characteristics
- •Active Supply Current
- •Idle Supply Current
- •Power-down Supply Current
- •Power-save Supply Current
- •Standby Supply Current
- •Pin Pull-up
- •Pin Driver Strength
- •Internal Oscillator Speed
- •Ordering Information
- •Packaging Information
- •Erratas
- •Datasheet Change Log for ATmega8
- •Changes from Rev. 2486K-08/03 to Rev. 2486L-10/03
- •Changes from Rev. 2486K-08/03 to Rev. 2486L-10/03
- •Changes from Rev. 2486J-02/03 to Rev. 2486K-08/03
- •Changes from Rev. 2486I-12/02 to Rev. 2486J-02/03
- •Changes from Rev. 2486H-09/02 to Rev. 2486I-12/02
- •Changes from Rev. 2486G-09/02 to Rev. 2486H-09/02
- •Changes from Rev. 2486F-07/02 to Rev. 2486G-09/02
- •Changes from Rev. 2486E-06/02 to Rev. 2486F-07/02
- •Changes from Rev. 2486D-03/02 to Rev. 2486E-06/02
- •Changes from Rev. 2486C-03/02 to Rev. 2486D-03/02
- •Changes from Rev. 2486B-12/01 to Rev. 2486C-03/02
- •Table of Contents
Changing Channel or Reference Selection
ATmega8(L)
Figure 94. ADC Timing Diagram, Free Running Conversion
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One Conversion |
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Next Conversion |
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Cycle Number |
11 |
12 |
13 |
1 |
2 |
3 |
4 |
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ADC Clock |
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ADSC |
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ADIF |
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ADCH |
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MSB of Result |
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ADCL |
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LSB of Result |
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Conversion |
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Sample &Hold |
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Complete |
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MUX and REFS |
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Update |
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Table 73. ADC Conversion Time
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Sample & Hold (Cycles |
Conversion Time |
Condition |
from Start of Conversion) |
(Cycles) |
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Extended conversion |
13.5 |
25 |
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Normal conversions, single ended |
1.5 |
13 |
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The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channels and reference selection only takes place at a safe point during the conversion. The channel and reference selection is continuously updated until a conversion is started. Once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Continuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after ADSC is written. The user is thus advised not to write new channel or reference selection values to ADMUX until one ADC clock cycle after ADSC is written.
If both ADFR and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX Register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. ADMUX can be safely updated in the following ways:
1.When ADFR or ADEN is cleared.
2.During conversion, minimum one ADC clock cycle after the trigger event.
3.After a conversion, before the Interrupt Flag used as trigger source is cleared.
When updating ADMUX in one of these conditions, the new settings will affect the next ADC conversion.
197
2486M–AVR–12/03