ATmega8(L)

Electrical Characteristics

Note: Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.

Absolute Maximum Ratings*

.................................Operating Temperature					-55°C to +125°C	*NOTICE: Stresses beyond those listed under “Absolute
						Maximum Ratings” may cause permanent dam-
Storage Temperature ....................................					-65°C to +150°C	age to the device. This is a stress rating only and
						functional operation of the device at these or
Voltage on any Pin except RESET						other conditions beyond those indicated in the
with respect to Ground ................................					- 0.5V to VCC+0.5V	operational sections of this specification is not
						implied. Exposure to absolute maximum rating
Voltage on RESET with respect to Ground					.....-0.5V to +13.0V	conditions for extended periods may affect
Maximum Operating Voltage					6.0V	device reliability.
DC Current per I/O Pin ...............................................					40.0 mA
DC Current VCC and GND Pins................................					200.0 mA

DC Characteristics

TA = -40°C to 85°C, VCC = 2.7V to 5.5V (unless otherwise noted)

Symbol

Parameter

Condition

Min

Typ

Max

Units

VIL

Input Low Voltage

Except XTAL1 pin

-0.5

(1)

V

0.2 VCC

VIL1

Input Low Voltage

XTAL1 pin, External Clock Selected

-0.5

(1)

V

0.1 VCC

(2)

VIH

Input High Voltage

Except XTAL1 and RESET pins

0.6 VCC

VCC

+ 0.5

V

VIH1

Input High Voltage

XTAL1 pin, External Clock Selected

0.8 VCC

(2)

VCC

+ 0.5

V

(2)

VIH2

Input High Voltage

RESET pin

0.9 VCC

VCC

+ 0.5

V

VOL

Output Low Voltage(3)

I

OL

= 20 mA, V

CC

= 5V

0.7

V

(Ports A,B,C,D)

IOL = 10 mA, VCC = 3V

0.5

V

VOH

Output High Voltage(4)

I

OH

= -20 mA, V

CC

= 5V

4.2

V

(Ports A,B,C,D)

IOH = -10 mA, VCC = 3V

2.2

V

IIL

Input Leakage

Vcc = 5.5V, pin low

1

µA

Current I/O Pin

(absolute value)

IIH

Input Leakage

Vcc = 5.5V, pin high

1

µA

Current I/O Pin

(absolute value)

RRST

Reset Pull-up Resistor

30

80

kΩ

Rpu

I/O Pin Pull-up Resistor

20

50

kΩ

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TA = -40°C to 85°C, VCC = 2.7V to 5.5V (unless otherwise noted) (Continued)

Symbol	Parameter	Condition	Min	Typ	Max	Units
		Active 4 MHz, VCC = 3V			5	mA
		(ATmega8L)
		Active 8 MHz, VCC = 5V			15	mA
	Power Supply Current	(ATmega8)
ICC		Idle 4 MHz, VCC = 3V			2	mA
		(ATmega8L)
		Idle 8 MHz, VCC = 5V			7	mA
		(ATmega8)
	Power-down mode(5)	WDT enabled, VCC = 3V			25	µA
		WDT disabled, VCC = 3V			2	µA
VACIO	Analog Comparator	VCC = 5V			20	mV
	Input Offset Voltage	Vin = VCC/2
IACLK	Analog Comparator	VCC = 5V	-50		50	nA
	Input Leakage Current	Vin = VCC/2
tACID	Analog Comparator	VCC = 2.7V		750		ns
	Propagation Delay	VCC = 4.0V		500

Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low

2.“Min” means the lowest value where the pin is guaranteed to be read as high

3.Although each I/O port can sink more than the test conditions (20mA at Vcc = 5V, 10mA at Vcc = 3V) under steady state conditions (non-transient), the following must be observed:

PDIP Package:

1] The sum of all IOL, for all ports, should not exceed 400 mA.

2] The sum of all IOL, for ports C0 - C5 should not exceed 200 mA.

3] The sum of all IOL, for ports B0 - B7, C6, D0 - D7 and XTAL2, should not exceed 100 mA. TQFP and MLF Package:

1] The sum of all IOL, for all ports, should not exceed 400 mA.

2] The sum of all IOL, for ports C0 - C5, should not exceed 200 mA.

3] The sum of all IOL, for ports C6, D0 - D4, should not exceed 300 mA.

4] The sum of all IOL, for ports B0 - B7, D5 - D7, should not exceed 300 mA.

If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition.

4.Although each I/O port can source more than the test conditions (20mA at Vcc = 5V, 10mA at Vcc = 3V) under steady state conditions (non-transient), the following must be observed:

PDIP Package:

1] The sum of all IOH, for all ports, should not exceed 400 mA.

2] The sum of all IOH, for port C0 - C5, should not exceed 100 mA.

3] The sum of all IOH, for ports B0 - B7, C6, D0 - D7 and XTAL2, should not exceed 100 mA. TQFP and MLF Package:

1] The sum of all IOH, for all ports, should not exceed 400 mA.

2] The sum of all IOH, for ports C0 - C5, should not exceed 200 mA.

3] The sum of all IOH, for ports C6, D0 - D4, should not exceed 300 mA.

4] The sum of all IOH, for ports B0 - B7, D5 - D7, should not exceed 300 mA.

If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition.

5.Minimum VCC for Power-down is 2.5V.

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External Clock Drive Figure 114. External Clock Drive Waveforms

Waveforms

VIH1

VIL1

External Clock Drive

Table 99. External Clock Drive

			VCC = 2.7V to 5.5V			VCC = 4.5V to 5.5V
Symbol	Parameter		Min		Max	Min		Max	Units
1/tCLCL	Oscillator Frequency		0		8	0		16	MHz
tCLCL	Clock Period		125			62.5			ns
tCHCX	High Time		50			25			ns
tCLCX	Low Time		50			25			ns
tCLCH	Rise Time				1.6			0.5	µs
tCHCL	Fall Time				1.6			0.5	µs
∆ tCLCL	Change in period from one				2			2	%
	clock cycle to the next
Table 100. External RC Oscillator, Typical Frequencies
	R [kΩ ](1)		C [pF]					f(2)
	100			47				87 kHz
	33			22				650 kHz
	10			22				2.0 MHz
Notes: 1.	R should be in the range 3 kΩ		- 100 kΩ	, and C should be at least 20 pF. The C values
	given in the table includes pin capacitance. This will vary with package type.
2. The frequency will vary with package type and board layout.

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Two-wire Serial Interface Characteristics

Table 101 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega8 Two-wire Serial Interface meets or exceeds these requirements under the noted conditions.

Timing symbols refer to Figure 115.

Table 101. Two-wire Serial Bus Requirements

Symbol		Parameter				Condition		Min	Max	Units
VIL		Input Low-voltage						-0.5	0.3 VCC	V
VIH		Input High-voltage						0.7 VCC	VCC + 0.5	V
	(1)	Hysteresis of Schmitt Trigger Inputs						(2)	–	V
Vhys								0.05 VCC
VOL(1)		Output Low-voltage				3 mA sink current		0	0.4	V
t	(1)	Rise Time for both SDA and SCL						20 + 0.1C (3)(2)	300	ns
	r							b
t	(1)	Output Fall Time from V	to V		10 pF < C < 400 pF(3)			20 + 0.1C (3)(2)	250	ns
	of	IHmin	ILmax				b	b
tSP(1)		Spikes Suppressed by Input Filter						0	50(2)	ns
Ii		Input Current each I/O Pin			0.1VCC < Vi < 0.9VCC			-10	10	µA
C (1)		Capacitance for each I/O Pin						–	10	pF
	i
f	SCL	SCL Clock Frequency		f	(4)	> max(16f , 250kHz)(5)		0	400	kHz
				CK			SCL
						fSCL ≤	100 kHz	VC C – 0,4V	1000ns	Ω
								----------------------------	------------------
Rp		Value of Pull-up resistor						3mA	Cb
						fSCL > 100 kHz		VC C – 0,4V	300ns	Ω
								----------------------------	---------------
								3mA	Cb
tHD;STA		Hold Time (repeated) START Condition				fSCL ≤	100 kHz	4.0	–	µs
						fSCL > 100 kHz		0.6	–	µs
tLOW		Low Period of the SCL Clock				fSCL ≤	100 kHz(6)	4.7	–	µs
						f > 100 kHz(7)		1.3	–	µs
						SCL
tHIGH		High period of the SCL clock				fSCL ≤	100 kHz	4.0	–	µs
						fSCL > 100 kHz		0.6	–	µs
tSU;STA		Set-up time for a repeated START condition				fSCL ≤	100 kHz	4.7	–	µs
						fSCL > 100 kHz		0.6	–	µs
tHD;DAT		Data hold time				fSCL ≤	100 kHz	0	3.45	µs
						fSCL > 100 kHz		0	0.9	µs
tSU;DAT		Data setup time				fSCL ≤	100 kHz	250	–	ns
						fSCL > 100 kHz		100	–	ns
tSU;STO		Setup time for STOP condition				fSCL ≤	100 kHz	4.0	–	µs
						fSCL > 100 kHz		0.6	–	µs
tBUF		Bus free time between a STOP and START				fSCL ≤	100 kHz	4.7	–	µs
		condition				fSCL > 100 kHz		1.3	–	µs

Notes: 1. In ATmega8, this parameter is characterized and not 100% tested.

2.Required only for fSCL > 100 kHz.

3.Cb = capacitance of one bus line in pF.

4.fCK = CPU clock frequency

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5.This requirement applies to all ATmega8 Two-wire Serial Interface operation. Other

devices connected to the Two-wire Serial Bus need only obey the general fSCL requirement.

6.The actual low period generated by the ATmega8 Two-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be greater than 6 MHz for the low time requirement to be

strictly met at fSCL = 100 kHz.

7. The actual low period generated by the ATmega8 Two-wire Serial Interface is (1/fSCL

- 2/fCK), thus the low time requirement will not be strictly met for fSCL > 308 kHz when fCK = 8 MHz. Still, ATmega8 devices connected to the bus may communicate at full

speed (400 kHz) with other ATmega8 devices, as well as any other device with a proper tLOW acceptance margin.

Figure 115. Two-wire Serial Bus Timing

tof

tHIGH

tr

SCL

tLOW

tLOW

tSU;STA

tHD;STA

tHD;DAT

t

SDA

SU;DAT

tSU;STO

tBUF

SPI Timing

See Figure 116 and Figure 117 for details.

Characteristics

Table 102. SPI Timing Parameters

Description

Mode

Min

Typ

Max

1

SCK period

Master

See Table 50

2

SCK high/low

Master

50% duty cycle

3

Rise/Fall time

Master

3.6

4

Setup

Master

10

5

Hold

Master

10

6

Out to SCK

Master

0.5 • tSCK

7

SCK to out

Master

10

8

SCK to out high

Master

10

9

SS low to out

Slave

15

ns

10

SCK period

Slave

4 • tck

11

SCK high/low(1)

Slave

2 • t

ck

12

Rise/Fall time

Slave

1.6

13

Setup

Slave

10

14

Hold

Slave

10

15

SCK to out

Slave

15

16

SCK to SS high

Slave

20

17

SS high to tri-state

Slave

10

18

SS low to SCK

Salve

2 • tck

Note:

1. In SPI Programming mode the minimum SCK high/low period is:

- 2tCLCL for fCK < 12 MHz

- 3tCLCL for fCK > 12 MHz

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Figure 116. SPI interface timing requirements (Master Mode)

SS

6

1

	SCK
	(CPOL = 0)
			2	2
	SCK
	(CPOL = 1)
	4	5		3
	MISO	MSB	...	LSB
	(Data Input)
			7	8
	MOSI	MSB	...	LSB
	(Data Output)

Figure 117. SPI interface timing requirements (Slave Mode)

	18
	SS
	9			10	16
	SCK
	(CPOL = 0)
			11	11
	SCK
	(CPOL = 1)
	13	14			12
	MOSI	MSB	...	LSB
	(Data Input)
			15		17
	MISO	MSB	...	LSB	X
	(Data Output)

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