14.1.10Timer/Counter1 Initialization for Asynchronous Mode

To change Timer/Counter1 to the asynchronous mode, first enable PLL, and poll the PLOCK bit until it is set, and then set the PCKE bit.

14.1.11Timer/Counter1 in PWM Mode

When the PWM mode is selected, Timer/Counter1 and the Output Compare Register C - OCR1C form a dual 8-bit, free-running and glitch-free PWM generator with outputs on the PB1(OC1A) and PB3(OC1B) pins and inverted outputs on pins PB0(OC1A) and PB2(OC1B). As default non-overlapping times for complementary output pairs are zero, but they can be inserted using a Dead Time Generator (see description on page 100).

Figure 14-4. The PWM Output Pair

PWM1x

PWM1x

t non-overlap=0 t non-overlap=0

x = A or B

When the counter value match the contents of OCR1A or OCR1B, the OC1A and OC1B outputs are set or cleared according to the COM1A1/COM1A0 or COM1B1/COM1B0 bits in the Timer/Counter1 Control Register A - TCCR1, as shown in Table 14-4.

Timer/Counter1 acts as an up-counter, counting from $00 up to the value specified in the output compare register OCR1C, and starting from $00 up again. A compare match with OC1C will set an overflow interrupt flag (TOV1) after a synchronization delay following the compare event.

	Table 14-4.	Compare Mode Select in PWM Mode
	COM11	COM10		Effect on Output Compare Pins
	0	0		OC1x not connected.
				OC1x not connected.
	0	1		OC1x cleared on compare match. Set whenTCNT1 = $01.
				OC1x set on compare match. Cleared when TCNT1 = $00.
	1	0		OC1x cleared on compare match. Set when TCNT1 = $01.
				OC1x not connected.
	1	1		OC1x Set on compare match. Cleared when TCNT1= $01.
				OC1x not connected.

Note that in PWM mode, writing to the Output Compare Registers OCR1A or OCR1B, the data value is first transferred to a temporary location. The value is latched into OCR1A or OCR1B when the Timer/Counter reaches OCR1C. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR1A or OCR1B. See Figure 14-5 for an example.

88 ATtiny25/45/85 Auto

7598C–AVR–09/06

ATtiny25/45/85 Auto

Figure 14-5. Effects of Unsynchronized OCR Latching

Compare Value changes

Counter Value

Compare Value

PWM Output OC1x

Synchronized OC1x Latch

Compare Value changes

Counter Value

Compare Value

	PWM Output OC1x
Unsynchronized OC1x Latch	Glitch

During the time between the write and the latch operation, a read from OCR1A or OCR1B will read the contents of the temporary location. This means that the most recently written value always will read out of OCR1A or OCR1B.

When OCR1A or OCR1B contain $00 or the top value, as specified in OCR1C register, the out- p ut P B1( OC 1A) or PB3 (OC1 B) is h eld lo w o r h ig h a cco rd in g to the se ttin gs of COM1A1/COM1A0. This is shown in Table 14-5.

Table 14-5. PWM Outputs OCR1x = $00 or OCR1C, x = A or B

COM1x1	COM1x0	OCR1x	Output OC1x	Output OC1x
0	1	$00	L	H
0	1	OCR1C	H	L
1	0	$00	L	Not connected.
1	0	OCR1C	H	Not connected.
1	1	$00	H	Not connected.
1	1	OCR1C	L	Not connected.

In PWM mode, the Timer Overflow Flag - TOV1 is set when the TCNT1 counts to the OCR1C value and the TCNT1 is reset to $00. The Timer Overflow Interrupt1 is executed when TOV1 is set provided that Timer Overflow Interrupt and global interrupts are enabled. This also applies to the Timer Output Compare flags and interrupts.

The frequency of the PWM will be Timer Clock 1 Frequency divided by (OCR1C value + 1). See the following equation:

fTCK1

= -----------------------------------

fPWM (OCR1C + 1)

89

7598C–AVR–09/06