eZ80® CPU User Manual
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Mixed-Memory Mode Applications
The eZ80® CPU contains a control bit flag that affects operation of interrupts, illegal instruction traps and restart (RST) instructions. The MixedADL (MADL) control bit must be set to 1 for all applications that run in both Z80 mode and ADL mode. The MADL control bit can be reset to 0 for all CPU applications that run exclusively in Z80 mode or exclusively in ADL mode. Default for the MADL control bit is reset to 0.
No application program can run exclusively in ADL mode, because the default for the CPU is to begin in Z80 mode. If a single JP.LIL instruction is used at or near the beginning of the source code to permanently change to ADL mode, this program is considered to operate exclusively in ADL mode.
The purpose of the MADL control bit is to force the CPU to monitor the memory mode when interrupts, traps or RST instructions occur. If the memory mode does not change, then the MADL control bit can be reset to 0.
When the MADL control bit is set to 1, the CPU pushes a byte onto the stack that contains the current memory mode whenever an interrupt, trap, or restart occurs. Even if the memory mode is not changed by the current interrupt, trap, or restart, the byte containing the memory mode bit is still pushed onto the stack. A 02h byte is pushed onto the stack if the current code is operating in Z80 mode. A 03h byte is pushed onto the stack if the current code is operating in ADL mode. The current memory mode is pushed onto the stack prior to setting the memory mode for the called service routine.
In addition, when the MADL control bit is set to 1 for mixedmemory mode applications, all interrupts begin in ADL mode.
For applications that run exclusively in a single memory mode (either Z80 or ADL mode), set the MADL control bit to 1. The CPU always handles interrupts, traps and restarts correctly if MADL is set to 1.
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eZ80® CPU User Manual
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The MADL control bit is set to 1 by the STMIX instruction. The MADL control bit is reset to 0 by the RSMIX instruction.
MIXED MEMORY Mode Guidelines
Applications that include legacy code that runs in Z80 mode, and new code that runs in ADL mode, must follow certain rules to ensure proper operation:
1.Include a STMIX instruction in the device initialization procedure that sets MADL to 1, ensuring that interrupt service routines begin in a consistent memory mode (ADL mode).
2.End all interrupt service routines with a RETI.L or RETN.L instruction to ensure that the interrupted code’s memory mode is popped from the SPL stack.
3.Use a suffixed CALL to access each block of code in the memory mode in which it was assembled or compiled. Suffixed JP instructions may also be used; however, suffixed CALL instructions are recommended, because the CPU keeps track of all the necessary memory modes when switching between blocks.
4.Any code block that may be called from either Z80 mode or ADL mode must be called with a suffix to save the calling code’s memory mode on the SPL stack.
5.Any routine that may be called from either mode must return with a suffixed RETI.L instruction to restore the calling code’s memory mode from the SPL stack.
6.If a calling code operating in one mode must pass stack-based operands/ arguments to a routine compiled or assembled for a different mode, it must use suffixed instructions to set up the operands/arguments. For PUSH, .S and .L suffixes control whether SPS or SPL is used and whether the operands/ arguments are stored as 2- or 3-byte values.
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Note: In mixed-ADL applications, some of these rules may represent exceptions to the eZ80® CPU’s design goal; i.e., that legacy code does not require modification to run on the eZ80® CPU. Assuming that legacy routines are not selectively converted to ADL mode and do not call newly-written routines, the only rule that could lead to such modification is Rule 5. If each legacy Z80 mode routine ends with a single RET.L at its end, this conversion is easy. Internal and conditional RETs require more careful review.
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PRELIMINARY Mixed-Memory Mode Applications |