eZ80® CPU User Manual

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Architectural Overview

The eZ80® CPU is ZiLOG's next-generation Z80 processor core. It is the basis of a new family of integrated microcontrollers and includes the following features:

•Upward code-compatible from Z80 and Z180 products

•Several address-generation modes, including 24-bit linear addressing

•24-bit registers and ALU

•8-bit data path

•Single-cycle fetch

•Pipelined fetch, decode, and execute

Processor Description

The eZ80® CPU is an 8-bit microcontroller that performs certain 16or 24-bit operations. A simplified block diagram of the CPU is illustrated in Figure 1. Understanding the separation between the control block and the data block is helpful toward understanding the two eZ80 memory modes—Z80 mode and ADDRESS AND DATA LONG (ADL) mode.

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I/O Control

	Control Block
DATA	Instruction
	Fetch
	Mode	Op Code
	Control	Decoder

Figure 1. eZ80® CPU Block Diagram

	Data Block
	CPU	Address	ADDR
	Registers	Generator
	ALU	Data	DATA
		Selector

Instruction Fetch

The instruction fetch block contains a state machine which controls the READs from memory. It fetches Op Codes and operands and keeps track of the start and end of each instruction. An instruction fetch block stores Op Codes during external memory READs and WRITEs. It also discards prefetched instructions when jumps, interrupts, and other control transfer events occur.

Mode Control

The Mode Control block of the CPU controls which mode the processor is currently operating in: HALT mode, SLEEP mode, Interrupt mode, debug mode, and ADL mode1.

1.The debug interface is discussed in greater detail in the eZ80 and eZ80Acclaim! product specifications.

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Op Code Decoder

The Op Codes are decoded within the CPU control block. After each instruction is fetched, it is passed to the decoder. The Op Code decoder is organized similarly to a large microcoded ROM.

CPU Registers

The CPU registers are contained within the CPU’s data block. Some are special purpose registers, such as the Program Counter, the Stack Pointer, and the Flags register. There are also a number of CPU control registers.

ALU

The Arithmetic Logic Unit (ALU) is contained within the CPU’s data block. The ALU performs the arithmetic and logic functions on the addresses and the data passed over from the control block or from the CPU registers.

Address Generator

The address generator creates the addresses for all CPU memory READ and WRITE operations. The address generator also contains the Z80 Memory Mode Base Address Register (MBASE) for address translation in Z80 mode operation.

Data Selector

The data selector places the appropriate data onto the data bus. The data selector controls the data path based on the instruction currently being executed.

Pipeline Description

The CPU pipeline reduces the overall cycle time for each instruction. In principle, each instruction must be fetched, decoded, and executed. This process normally spans at least 3 cycles. The CPU pipeline, however, can reduce the overall time of some instructions to as little as 1 cycle by

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allowing the next instruction to be prefetched and decoded while it executes the current instruction as illustrated in Figure 2. The CPU can operate on multiple instructions simultaneously to improve operating efficiency.

System Clock
Instruction 1
	Fetch	Decode	Execute
Instruction 2		Fetch	Decode	Execute
Instruction 3			Fetch	Decode	Execute

Figure 2. Pipeline Overview

In Figure 1, the pipelining process is demonstrated using a series of instructions. The first LD instruction prefetches its Op Code and first operand during the decode and execute phases of the preceding INC instruction. However, the second LD instruction in the sequence only prefetches its Op Code. The bus WRITE during the execute phase of the first LD instruction prevents the pipeline from prefetching the first operand of the next instruction. Thus, the number of bytes prefetched is a function of the command currently executing in the CPU.

When a control transfer takes place, the Program Counter (PC) does not progress sequentially. Therefore, the pipeline must be flushed. All prefetched values are ignored. Control transfer can occur because of an interrupt or during execution of a Jump (JP), CALL, Return (RET), Restart (RST), or similar instruction. After the control transfer instruction is executed, the pipeline must start over to fetch the next operand.

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Clock
Address	PC	PC+1	PC+2	PC+3	PC+4	PC+5	1234h	PC+6	PC+7	5678h
Data In	3Ch	32h	34h	12h	32h	(1234h) 78h		56h	3Ch	(5678h)
	INC A	LD (nn), A nL		nH	LD (nn), A Write		nL	nH	INC A	Write
Command
Execution					Next command				Next command
State				1 clock delay for execution				1 clock delay for execution
INC A	Fetch	Decode	Execute
LD (1234h), A	Prefetch		F & D	F & D	Decode	Execute
LD (5678h), A					Prefetch		F & D	F & D	Decode	Execute
INC A									Prefetch
Data Out			Invalid			Valid		Invalid		Valid

INST_READ

MEM_READ

MEM_WRITE

Note: F & D = Fetch & Decode

Figure 1. Pipeline Example

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